ES-100M / QS-100M Multi-port Asynchronous Communications Adapter User's Manual QUATECH, INC.
ES-100 User's Manual Version 2.00 October 1994 P/N.
WARRANTY INFORMATION Quatech Inc. warrants the ES-100M / QS-100M to be free of defects for one (1) year from the date of purchase. Quatech Inc. will repair or replace any adapter that fails to perform under normal operating conditions and in accordance with the procedures outlined in this document during the warranty period. Any damage that results from improper installation, operation, or general misuse voids all warranty rights.
TABLE OF CONTENTS List of Figures I. II. III. IV. V. VI. VII. VIII.
LIST OF FIGURES Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25.
I. GENERAL INFORMATION The Quatech, Inc. ES-100M provides eight RS-232 asynchronous serial communication interfaces for IBM-compatible personal computer systems using the 16-bit ISA (Industry Standard Architecture) expansion bus. The QS-100M is a four-port version of the same product (with several blank areas on the circuit card). External connections are made using RJ-11 "phone jack" connectors. This document uses "QS/ES-100M" when information applies to either product.
II. INSTALLATION If the default address and interrupt settings are sufficient, the QS/ES-100M can be quickly installed and put to use. The factory defaults are listed in Figure 1.
Figure 2 --- Diagram of QS/ES-100M (SW1, SW2) Set addresses here SW2 J8 J9 J6 J7 J4 J5 J2 J3 (J10) Set IRQ level here QUATECH INC. ES-100 / QS-100M 16450/16550 16450/16550 16450/16550 Shaded parts are not present on the QS-100M.
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III. ADDRESSING PORTS Setting The Address The base address of the QS/ES-100M is set using the two DIP switch packs. When setting the address selection switches, a switch in the "ON" position specifies that the corresponding address line must be a logic 0 for the port to be selected. Similarly, a switch in the "OFF" position forces the corresponding address line to be a logic 1 for the port to be selected.
Switch SW1 and the first four positions of switch SW2 select address lines A15 through A6. The fifth position of SW2 selects address line A5 on the QS-100M and is not used on the ES-100M. This reflects the different I/O space requirements of the two products. The remaining address lines, A4 - A0 for the QS-100M, or A5 - A0 for the ES-100M, are used by the UART to select the register being accessed. The sixth position on SW2 is used to enable or disable the interrupt status register (see page 9).
Switch on bit = 0 Switch off bit = 1 QS-100M Position 6 of SW2 is used to enable or disable the interrupt status register. Factory default setting --- 0300 hex SW1 SW2 ON 1 2 3 4 5 6 1 2 3 4 5 0 0 0 0 0 0 2 1 0 0 0 (no digits) 0 0 3 0 6 Another Example --- 5AC0 hex SW1 SW2 ON 1 2 3 4 5 6 1 2 3 4 5 0 4 0 1 8 0 2 0 8 4 0 (no digits) C A 5 6 0 ES-100M Position 6 of SW2 is used to enable or disable the interrupt status register.
IV. INTERRUPT LEVEL (IRQ) IRQ11 IRQ12 IRQ14 IRQ15 10 11 12 13 14 15 16 3 4 5 1 2 6 IRQ10 9 IRQ7 22 IRQ6 21 IRQ5 20 IRQ4 17 18 19 IRQ3 IRQ2 The QS/ES-100M allows the use of any interrupt level in the range IRQ2 to IRQ7, IRQ10 to IRQ12, IRQ14, or IRQ15, selected using jumper pack J10. (Early versions of the QS/ES-100M are limited to IRQ2-7.) In Figure 6, the factory default setting of IRQ3 is shown. To select a different IRQ, move the jumper to the appropriate position on J10.
The choice of using the interrupt status register or the UART scratchpads (factory default) is made using position 6 of switch SW2 as shown in Figure 7. SW2 SW2 ON ON 1 2 3 4 5 1 6 2 3 4 5 6 Scratchpad Register (factory default) Interrupt Status Register Slide position 6 of SW2 toward the top of the QS/ES-100M to enable the interrupt status register, or toward the bottom of the QS/ES-100M to disable it.
V. EXTERNAL CONNECTIONS RS-232-C devices are classified by their function as either Data Terminal Equipment (DTE) or Data Communication Equipment (DCE). Generally, data terminal equipment is defined as the communication source and data communication equipment is defined as the device that provides a communication channel between two DTE-type devices.
Channel Output Configuration The QS/ES-100M connects to peripheral equipment through RJ-11 connectors, or using the optional adapter cables, male D-25 connectors. When the RJ-11 connector is converted to a D-25 connector, the conversion cable must be assembled with respect to either a DTE or DCE configuration. The standard serial port connections are listed in Figure 11.
The AUXIN and AUXOUT signals on the RJ-11 connector must be determined as well. AUXIN may be selected to be either CTS or DSR. AUXOUT may be selected to be either RTS or DTR. The decision of which signals to use is made separately for each channel. Figure 13 --- Auxiliary signal configuration jumpers.
A feature available on the ES/QS-100M revision B and newer is the ability to input the carrier detect (DCD) signal from the RJ-11 connector. When shipped from the factory, the ES/QS-100M is configured for compatibility with revision 'A' of the adapter as shown in Figure 14(A) below. In this configuration, pin 3 of the RJ-11 is connected to chassis ground i.e. the frame of the PC.
VI. SERIAL PORT FUNCTIONAL DESCRIPTION This section contains information intended for advanced users planning to do custom programming with the QS/ES-100M. The information presented here is a technical description of the interface to the 16450 or 16550 UART. The 16450 UART is an improved functional equivalent of the 8250 UART, performing serial-to-parallel conversion on received data and parallel-to-serial conversion on output data.
Accessing The Serial Port Registers Figure 15 lists the address map for the 16450 and 16550 UARTs. Each register can be accessed by reading from or writing to the proper I/O address. This I/O address is determined by adding an offset to the base address set for the particular serial port. The base address is set using DIP switches on the QS/ES-100M (see section III). Notice that two locations access different registers depending on whether an I/O read or I/O write is attempted.
Interrupt Enable Register This register is located at I/O address [base+1]. It enables the five types of UART interrupts. Interrupts can be totally disabled by setting all of the enable bits in this register to a logic 0. Setting any bit to a logic 1 enables that particular interrupt.
BIT DESCRIPTION 7 FFE --- FIFO enable: (16550 only) When logic 1, indicates FIFO mode enabled. Always logic 0 for the 16450. 6 FFE --- FIFO enable: (16550 only) When logic 1, indicates FIFO mode enabled. Always logic 0 for the 16450. 5 0 --- reserved 4 0 --- reserved 3 IID2 --- 2 IID1 --- 1 IID0 --- 0 IP --- Interrupt pending: When logic 0, indicates that an interrupt is pending and the contents of the interrupt identification register may be used to determine the interrupt source.
Fifo Control Register (16550 Only) This register, which applies only to the 16550 UART, is a write-only register located at I/O address [base+2]. It is used to enable the FIFO mode, clear the FIFOs, set the threshold level for the receive FIFO to generate interrupts, and to set the mode under which the device uses DMA. Note that DMA mode is NOT supported by the QS/ES-100M.
Line Control Register This register is located at I/O address [base+3]. It is used for specifying the format of the asynchronous serial data to be processed by the UART, and to set the Divisor Latch Access Bit (DLAB) allowing access to the baud rate divisor latches. BIT DESCRIPTION 7 DLAB --- Divisor latch access bit: DLAB must be set to logic 1 to access the baud rate divisor latches. DLAB must be set to logic 0 to access the receiver buffer, transmitting holding register and interrupt enable register.
Modem Control Register This register is located at I/O address [base+4], and is used to control the interface with the modem or device used in place of a modem. This register allows the states of the "modem control signals" to be changed. These are DTR (Data Terminal Ready) and RTS (Request To Send). It is also possible to place the UART in a loopback mode for testing. Finally, the user-defined outputs OUT1 and OUT2 are controlled from this register.
Line Status Register This register is located at I/O address [base+5]. It is used to provide various types of status information concerning the data transfer. As Figure 22 shows, the Line Status Register indicates several types of errors, an empty transmit buffer, a ready receive buffer, or a break on the receive line. BIT DESCRIPTION 7 FFRX --- Error in RCVR FIFO (16550 FIFO mode only): Always logic 0 in 16450 or 16550 non-FIFO mode.
Modem Status Register This register is located at I/O address [base+6]. It reports on the status of signals coming from the modem or equipment used in place of a modem. It allows the current states of "modem control signals" to be sensed. These signals include the DCD (Data Carrier Detect), RI (Ring Indicator), DSR (Data Set Ready), and CTS (Clear To Send). The Modem Status Register also provides change information for each of these signals.
FIFO Interrupt Mode Operation (16550 UART Only) When The Receiver Fifo And Receiver Interrupts Are Enabled: 1. The receive data interrupt is issued when the receive FIFO reaches the trigger level. The interrupt is cleared as soon as the receive FIFO falls below the trigger level. 2. The Interrupt Identification Register's receive data available indicator is set and cleared along with the receive data interrupt when the receive FIFO falls below the trigger level. 3.
FIFO Polled Mode Operation (16550 UART Only) The receiver and transmitter are operated independently, which would allow either or both to be used in a polled mode rather than using interrupts to determine when the UART needs to be serviced. To use the UART in a polled mode, the software is responsible for continuously checking for the conditions that normally cause interrupts to occur. This would be done using the Line Status Register. 1.
Baud Rate Selection The 16450 or 16550 UART determines the baud rate of the serial output using a combination of the clock input frequency and the value written to the divisor latches. Standard personal computer serial interfaces use an input clock of 1.8432 MHz. To increase versatility, the QS/ES-100M uses an 18.432 MHz crystal and a frequency divider circuit to produce the standard clock frequency. Jumper block J1 is used to set the frequency input to the UART.
DESIRED BAUD RATE DIVISOR LATCH VALUE ERROR BETWEEN DESIRED AND ACTUAL VALUES (%) 50 2304 - 75 1536 - 110 1047 0.026 150 768 - 300 384 - 600 192 - 1200 96 - 1800 64 - 2000 58 0.69 2400 48 - 3600 32 - 4800 24 - 7200 16 - 9600 12 - 19200 6 - 38400 3 - 56000 2 2.86 Figure 25 --- Divisor Latch settings for common baud rates using 1.
VII. SPECIFICATIONS Bus interface: Industry Standard Architecture (ISA) 16-bit bus IBM PC-ATTM compatible Dimensions: Serial ports Number of ports: 13.4" x 4.
VIII. TROUBLESHOOTING Listed here are some common problems and frequent causes of those problems. Suggestions for corrective action are given. If the information here does not provide a solution, contact Quatech Customer Service for technical support. Any unauthorized repairs or modifications will void the QS/ES-100M's warranty. Computer will not boot up. 1. Is the QS/ES-100M properly inserted? Remove the card and try again. Perhaps try a different expansion slot. 2.
