User`s manual

FIFO polled mode operation (16550 UART only)
The receiver and transmitter are operated independently, which would allow
either or both to be used in a polled mode rather than using interrupts to determine
when the UART needs to be serviced.
To use the UART in a polled mode, the software is responsible for continuously
checking for the conditions that normally cause interrupts to occur. This would be done
using the Line Status Register.
1. The Data Ready bit will be set to logic 1 whenever there is at least one byte in
the receive FIFO.
2. Errors can be detected using the various error bits.
3. The Transmitter Holding Register Empty bit can be used to determine when the
transmit FIFO is empty.
4. The Transmitter Empty bit indicates that the transmitter shift register is empty as
well as the transmit FIFO being empty.
5. Trigger levels and FIFO timeouts do not apply. Both FIFOs are fully capable
of holding multiple characters at any time.
22 Quatech ES-100D User's Manual