User`s manual

FIFO INTERRUPT MODE OPERATION (16550 UART only)
When the receiver FIFO and receiver interrupts are enabled:
1. The receive data interrupt is issued when the receive FIFO reaches the trigger
level. The interrupt is cleared as soon as the receive FIFO falls below the
trigger level.
2. The Interrupt Identification Register's receive data available indicator is set and
cleared along with the receive data interrupt when the receive FIFO falls below
the trigger level.
3. The data ready indicator is set as soon as a character is transferred into the
receiver FIFO and is cleared when the FIFO is empty.
4. A FIFO timeout interrupt will occur if the receive FIFO contains at least one
character, at least four character-times have passed since receipt of the last
character, and the last read of the FIFO by the CPU was done more than four
character-times ago.
5. Timeout interrupts are cleared when a read of the receive FIFO is done.
6. The receive FIFO timeout timer is reset whenever a new character is received
into the FIFO or a read of the FIFO is done.
When the transmit FIFO and transmit interrupts are enabled:
1. The transmitter holding register empty interrupt occurs when the transmit FIFO
is empty, and is cleared when a character is written to the FIFO or when the
Interrupt Identification Register is read.
2. Transmitter FIFO empty indications are delayed by one character-time less the
last stop bit time when the transmitter holding register is empty and there have
not been at least two bytes together in the transmit FIFO since the last time the
transmitter holding register was empty.
3. The first transmitter interrupt after enabling the FIFO mode will be immediate if
that interrupt is enabled.
Quatech ES-100D User's Manual 21