. GENERAL INFORMATION The Quatech, Inc. ES-100D provides eight RS-232 asynchronous serial communication interfaces for IBM-compatible personal computer systems using the 16-bit ISA (Industry Standard Architecture) expansion bus. The ES-100D's serial ports are implemented using 16450 Universal Asynchronous Receiver/Transmitters (UARTs). For higher performance, 16550 UARTs can be installed in place of the 16450 UARTs. The 16550 contains a hardware buffer that reduces processing overhead.
II. INSTALLATION If the default address and interrupt settings are sufficient, the ES-100D can be quickly installed and put to use. The factory defaults are listed in Figure 1. PORT ADDRESS IRQ Serial 1 300 hex 3 Serial 2 308 hex 3 Serial 3 310 hex 3 Serial 4 318 hex 3 Serial 5 320 hex 3 Serial 6 328 hex 3 Serial 7 330 hex 3 Serial 8 338 hex 3 Figure 1 --- Default address and IRQ settings for ES-100D The output of the ES-100D is a 78-pin D-connector.
Figure --- Diagram of ES-100D (SW1, SW2) Set addresses here QUATECH INC.
. ADDRESSING PORTS Setting the address The base address of the ES-100D is set using the two DIP switch packs. When setting the address selection switches, a switch in the "ON" position specifies that the corresponding address line must be a logic 0 for the port to be selected. Similarly, a switch in the "OFF" position forces the corresponding address line to be a logic 1 for the port to be selected.
A serial port's address is a 16-bit quantity that is most often expressed in four hexadecimal (base 16) digits. A hex digit can hold a value from 0 to 15 (decimal), and is made up of four binary bits given weights of eight, four, two, and one, hence the maximum value of 8+4+2+1 = 15. A possible serial port address is 5240 hex. The example below shows how the hex digits are broken down into binary bits.
. INTERRUPT LEVEL (IRQ) IRQ10 IRQ15 IRQ7 IRQ14 IRQ6 15 16 17 3 4 5 6 2 IRQ12 IRQ5 14 1 IRQ11 IRQ4 12 13 IRQ2 IRQ3 The ES-100D allows the use of any interrupt level in the range IRQ2 to IRQ7, IRQ10 to IRQ12, IRQ14, or IRQ15, selected using jumper pack J2. In Figure 6, the factory default setting of IRQ3 is shown. To select a different IRQ, move the jumper to the appropriate position on J2.
SW2 SW2 ON ON 1 2 3 4 5 6 1 Interrupt Status Register 2 3 4 5 6 Scratchpad Register Slide position 6 of SW2 toward the top of the ES-100D to enable the interrupt status register, or toward the bottom of the ES-100D to disable it. Figure --- Enabling the Interrupt Status Register When a hardware interrupt occurs, reading the interrupt status register will return the interrupt status of the entire ES-100D, as shown in Figure 8.
(This page intentionally left blank.
. EXTERNAL CONNECTIONS RS-232-C devices are classified by their function as either Data Terminal Equipment (DTE) or Data Communication Equipment (DCE). Generally, data terminal equipment is defined as the communication source and data communication equipment is defined as the device that provides a communication channel between two DTE-type devices.
Channel Output Configuration The ES-100D connects to peripheral equipment through a single female D-78 connector, or using the adapter cable, eight male D-25 connectors. The standard serial port connections are listed in Figure 11. Unlisted pins are not used and not connected.
1 40 21 2 60 41 22 3 4 61 42 23 43 24 5 63 12 64 11 65 10 66 9 67 8 68 7 69 6 70 5 71 4 72 3 45 26 7 46 27 8 47 28 9 48 29 10 49 30 11 50 31 12 51 32 13 52 33 14 53 34 15 73 54 35 16 74 25 24 23 22 21 20 19 18 17 16 15 2 14 1 55 36 56 37 18 75 76 57 38 19 D-25 connectors on the adapter cable 77 58 39 20 13 44 25 6 17 62 59 78 D-78 connector Dashed lines delineate channels Pins 25, 30, 35, 64, 69, 74 unused Figure --- ES-100D output connector
. SERIAL PORT FUNCTIONAL DESCRIPTION This section contains information intended for advanced users planning to do custom programming with the ES-100D. The information presented here is a technical description of the interface to the 16450 or 16550 UART. The 16450 UART is an improved functional equivalent of the 8250 UART, performing serial-to-parallel conversion on received data and parallel-to-serial conversion on output data.
Accessing the Serial Port registers Figure 13 lists the address map for the 16450 and 16550 UARTs. Each register can be accessed by reading from or writing to the proper I/O address. This I/O address is determined by adding an offset to the base address set for the particular serial port. The base address is set using DIP switches on the ES-100D (see section III). Notice that two locations access different registers depending on whether an I/O read or I/O write is attempted.
INTERRUPT ENABLE REGISTER This register is located at I/O address [base+1]. It enables the five types of UART interrupts. Interrupts can be totally disabled by setting all of the enable bits in this register to a logic 0. Setting any bit to a logic 1 enables that particular interrupt.
BIT DESCRIPTION 7 FFE --- FIFO enable:(16550 only) When logic 1, indicates FIFO mode enabled. Always logic 0 for the 16450. 6 FFE --- FIFO enable:(16550 only) When logic 1, indicates FIFO mode enabled. Always logic 0 for the 16450. 5 0 --- reserved 4 0 --- reserved 3 IID2 --- 2 IID1 --- 1 IID0 --- 0 IP --- Interrupt pending: When logic 0, indicates that an interrupt is pending and the contents of the interrupt identification register may be used to determine the interrupt source.
FIFO CONTROL REGISTER (16550 only) This register, which applies only to the 16550 UART, is a write-only register located at I/O address [base+2]. It is used to enable the FIFO mode, clear the FIFOs, set the threshold level for the receive FIFO to generate interrupts, and to set the mode under which the device uses DMA. Note that DMA mode is NOT supported by the ES-100D.
LINE CONTROL REGISTER This register is located at I/O address [base+3]. It is used for specifying the format of the asynchronous serial data to be processed by the UART, and to set the Divisor Latch Access Bit (DLAB) allowing access to the baud rate divisor latches. BIT DESCRIPTION 7 DLAB --- Divisor latch access bit: DLAB must be set to logic 1 to access the baud rate divisor latches. DLAB must be set to logic 0 to access the receiver buffer, transmitting holding register and interrupt enable register.
MODEM CONTROL REGISTER This register is located at I/O address [base+4], and is used to control the interface with the modem or device used in place of a modem. This register allows the states of the "modem control signals" to be changed. These are DTR (Data Terminal Ready) and RTS (Request To Send). It is also possible to place the UART in a loopback mode for testing. Finally, the user-defined outputs OUT1 and OUT2 are controlled from this register.
LINE STATUS REGISTER This register is located at I/O address [base+5]. It is used to provide various types of status information concerning the data transfer. As Figure 20 shows, the Line Status Register indicates several types of errors, an empty transmit buffer, a ready receive buffer, or a break on the receive line. BIT DESCRIPTION 7 FFRX --- Error in RCVR FIFO (16550 FIFO mode only): Always logic 0 in 16450 or 16550 non-FIFO mode.
MODEM STATUS REGISTER This register is located at I/O address [base+6]. It reports on the status of signals coming from the modem or equipment used in place of a modem. It allows the current states of "modem control signals" to be sensed. These signals include the DCD (Data Carrier Detect), RI (Ring Indicator), DSR (Data Set Ready), and CTS (Clear To Send). The Modem Status Register also provides change information for each of these signals.
FIFO INTERRUPT MODE OPERATION (16550 UART only) When the receiver FIFO and receiver interrupts are enabled: 1. The receive data interrupt is issued when the receive FIFO reaches the trigger level. The interrupt is cleared as soon as the receive FIFO falls below the trigger level. 2. The Interrupt Identification Register's receive data available indicator is set and cleared along with the receive data interrupt when the receive FIFO falls below the trigger level. 3.
FIFO polled mode operation (16550 UART only) The receiver and transmitter are operated independently, which would allow either or both to be used in a polled mode rather than using interrupts to determine when the UART needs to be serviced. To use the UART in a polled mode, the software is responsible for continuously checking for the conditions that normally cause interrupts to occur. This would be done using the Line Status Register. 1.
BAUD RATE SELECTION The 16450 or 16550 UART determines the baud rate of the serial output using a combination of the clock input frequency and the value written to the divisor latches. Standard personal computer serial interfaces use an input clock of 1.8432 MHz. A table of baud rates available is given in Figure 22. DESIRED BAUD RATE DIVISOR LATCH ERROR BETWEEN DESIRED AND ACTUAL VALUE VALUES (%) 50 2304 - 75 1536 - 110 1047 0.
. SPECIFICATIONS Bus interface: Industry Standard Architecture (ISA) 16-bit bus IBM PC-ATTM compatible Dimensions: 13.4" x 4.
. TROUBLESHOOTING Listed here are some common problems and frequent causes of those problems. Suggestions for corrective action are given. If the information here does not provide a solution, contact Quatech Customer Service for technical support. Any unauthorized repairs or modifications will void the ES-100D's warranty. Computer will not boot up. 1. Is the ES-100D properly inserted? Remove the card and try again. Perhaps try a different expansion slot. 2.
