Specifications
1.800.553.1170
Communication Overview
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CompactPCI boards must follow one of two size specifications
and have ejector handles that are IEEE 1101.10 compliant. 3U
boards measure 100mm x 160mm, and 6U boards measure
233.53mm x 160mm. The 3U boards have a single ejector handle
and use a 220 pin connector for all power, ground, and all 32-
and 64-bit PCI signals. This connector consists of two halves -
the lower half (110 pins) is called J1 and the upper half (also 110
pins) is called J2. Twenty pins are reserved for future use. 3U
boards that only perform 32-bit transfers can use a single 110
pin connector (J1). For example, Quatech's QSCP-100 serial
CompactPCI serial board (see page 70) is a 32-bit 3U board
using a single J1 connector. Both 32-bit and 64-bit 3U boards
can be mixed on a single CompactPCI backplane.
Ejector Handle
110 pin J1 Connector
(Quatech QSCP-100, 3U CompactPCI board)
160.00 mm
J5 J4
J3
J2
J1
233.35 mm
100.00 mm
(CompactPCI form factors for 3U and 6U boards)
6U boards can have up to three additional connectors (J3-J5)
with a total of 315 2mm style pins, and because of their large
size use two ejector handles. The CompactPCI specification only
defines signal-pin assignments for J1 and J2. J-3 through 5 can
be user defined based on application requirements. They can
also be used as a bridge to other buses like VME or ISA in hybrid
backplanes. PICMG is developing future specifications for a
standardized use of the additional connectors.
CompactPCI Systems
The CompactPCI system is made up of CompactPCI bus segments,
each of which has one system slot and up to seven slots for
CompactPCI peripherals (at 33MHz). The system slot is used to
control the peripherals attached to the bus segment. For example,
it provides bus arbitration, clocking, and reset functions, as well
as system initialization functions. It can be located at any position
in the backplane, and must use both J1 and J2 to control both
32-bit and 64-bit peripheral boards. The peripherals in the
remaining seven slots can be simple boards, intelligent slaves or
PCI bus masters. By using PCI-PCI bridge chips, the CompactPCI
bus can be expanded in 8 slot increments.
Peripherals attached to the first four PCI connectors are provided
a unique PCI interrupt. After that, rotating interrupts are
assigned to allow boards to share interrupts. The System
Slot board always has its own interrupt. Rules for interrupt
sharing are derived from the specification governing PCI
bridges. Note that because some devices require more
than one interrupt, interrupt sharing may be required even
if only the first four slots are used.
CompactPCI is designed to use both +5V, and +3.3V devices.
+V(I/O) power pins are designed for universal boards that can
operate at either +5V or +3.3V. A keying technology is used to
prevent a board from being attached to the wrong power pins.
Universal boards are not keyed. Backplanes have both +5V and
+3.3V, and, depending on the application, Universal boards can
use either. Typically, for 5V operation a brilliant blue coding
plug is used on the backplane, for 3.3 V operation a Cadmium
yellow coding plug is used. Power terminals can be located on
the front, rear or side of the backplane.
CompactPCI for Data Communication
CompactPCI boards are designed for ruggedized, industrial
environments. They are also ideal for many embedded systems
that are implemented in such environments. Though they are
electrically similar to standard PCI boards, CompactPCI boards
cannot be used in a desktop computer without a special adapter
board. They are made to be used in specialized enclosures
designed to provide both superior protection against
environmental hazards and easy access for rewiring, replacing,
or exchanging peripherals. To that end the pin sequence on the
backplane connector is staged to support hot swapping.
Quatech serial PCI boards with the "IND" option are also designed
for use in industrial environments. However, to implement
protection on the board itself requires sacrificing speed. The
CompactPCI specification is specifically designed for such
environments, and can optimally implement data communication
peripherals in them.