Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.
Quantum reserves the right to make changes and improvements to its products, without incurring any obligation to incorporate such changes or improvements into units previously sold or shipped. You can request Quantum publications from your Quantum Sales Representative or order them directly from Quantum. Publication Number: 81-121729-04 UL/CSA/TUV/CE UL standard 1950 recognition granted under File No. E78016 CSA standard C22.2 No. 950 certification granted under File No.
Table of Contents Chapter 1 ABOUT THIS MANUAL 1.1 1.2 1.3 1.4 AUDIENCE ................................................................................................................. MANUAL ORGANIZATION..................................................................................... TERMINOLOGY AND CONVENTIONS ................................................................. REFERENCES.............................................................................................................
Table of Contents 3.9.2 The 8.4-Gigabytes Barrier ................................................................................. 3-16 3.9.3 Operating system limitations ............................................................................ 3-16 3.10 SYSTEM STARTUP AND OPERATION ................................................................. 3-17 Chapter 4 SPECIFICATIONS 4.1 4.2 4.3 4.4 4.5 SPECIFICATION SUMMARY ...................................................................................
Table of Contents Chapter 6 ATA BUS INTERFACE AND ATA COMMANDS 6-1 6.1 INTRODUCTION ....................................................................................................... 6-1 6.2 SOFTWARE INTERFACE.......................................................................................... 6-1 6.3 MECHANICAL DESCRIPTION ................................................................................ 6-1 6.3.1 Drive Cable and Connector ..........................................................
List of Figures Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 3-6 Figure 3-7 Mechanical Dimensions of Quantum Fireball Plus AS Hard Disk Drive ......3-1 Drive Packing Assembly .................................................................................3-2 Drive Packing Assembly of a Polypropylene 20-Pack Container ...................3-3 Jumper Locations for the Quantum Fireball Plus AS Hard Disk Drive ........3-4 Jumper Locations on the Interface Connector ............................
List of Tables Table 3-1 Table 3-2 Table 3-3 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 4-6 Table 4-7 Table 4-8 Table 4-9 Table 5-1 Table 5-2 Table 6-1 Table 6-2 Table 6-3 Table 6-4 Table 6-5 Table 6-6 Table 6-7 Table 6-8 Table 6-9 Table 6-10 Table 6-11 Table 6-12 Table 6-13 Table 6-14 Table 6-15 Table 6-16 Table 6-17 Table 6-18 Table 6-19 Table 6-20 Table 6-21 Table 6-22 Table 6-23 Table 6-24 Table 6-25 Table 6-26 Table 6-27 AT Jumper Options..................................................
Table of Contents Table 6-28 Table 6-29 Table 6-30 Table 6-31 Table 6-32 DEFECT LIST DATA FORMAT .......................................................................... DEFECT ENTRY DATA FORMAT...................................................................... Accessing the READ CONFIGURATION Command.......................................... Accessing the SET CONFIGURATION Command ............................................. Accessing the SET CONFIGURATION WITHOUT SAVING TO DISK Command............
Chapter 1 ABOUT THIS MANUAL This chapter gives an overview of the contents of this manual, including the intended audience, how the manual is organized, terminology and conventions, and references. 1.1 AUDIENCE The Quantum Fireball Plus ASM™10.2/20.5/30.0/40.0/60.0 GB AT Product Manual is intended for several audiences. These audiences include: the end user, installer, developer, original equipment manufacturer (OEM), and distributor.
About This Manual • ECC error correcting code • fci flux changes per inch • Hz hertz • KB kilobytes • LSB least significant bit • mA milliamperes • MB megabytes (1 MB = 1,000,000 bytes when referring to disk storage and 1,048,576 bytes in all other cases) • Mbit/s megabits per second • MB/s megabytes per second • MHz megahertz • ms milliseconds • MSB most significant bit • mV millivolts • ns nanoseconds • tpi tracks per inch • µs microseconds • V volts The typographical an
About This Manual Naming Conventions: • Host: In general, the system in which the drive resides is referred to as the host. • Computer Voice: This refers to items you type at the computer keyboard. These items are listed in 10-point, all capitals, Courier font. An example is FORMAT C:/S. 1.4 REFERENCES For additional information about the AT interface, refer to: • IBM Technical Reference Manual #6183355, March 1986. • ATA Common Access Method Specification, Revision 5.0. Quantum Fireball Plus AS 10.
About This Manual 1-4 Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.
Chapter 2 GENERAL DESCRIPTION This chapter summarizes the general functions and key features of the Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.0 GB AT hard disk drives, as well as the applicable standards and regulations. 2.5 PRODUCT OVERVIEW Quantum’s Fireball Plus AS hard disk drives are part of a family of high performance, 1-inch-high hard disk drives manufactured to meet the highest product quality standards.
General Description Performance • Average seek time of 8.5 ms • Average rotational latency of 4.17 ms • New Ultra ATA interface with Quantum-patented Ultra ATA/100 protocol supporting burst data transfer rates of 100 MB/s. • 2 MB buffer with 1.9 MB (approximate) Advance Cache Management (ACM).
General Description 2.7 Regulatory Compliance Standards Quantum Corporation’s disk drive products meet all domestic and international product safety regulatory compliance requirements. Quantum’s disk drive products conform to the following specifically marked Product Safety Standards: • Underwriters Laboratories (UL) Standard 1950. This certificate is a category certification pertaining to all 3.5-inch series drives models. • Canadian Standards Association (CSA) Standard C.22.2 No. 1950.
General Description 2-8 Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.
Chapter 3 INSTALLATION This chapter explains how to unpack, configure, mount, and connect the Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.0 GB AT hard disk drive prior to operation. It also explains how to start up and operate the drive. 3.1 SPACE REQUIREMENTS The Quantum Fireball Plus AS hard disk drives are shipped without a faceplate. Figure 3-1 shows the external dimensions of the Quantum Fireball Plus AS 10.2/ 20.5/30.0/40.0/60.0 GB AT drives. 26.1 mm (max) (1.00 inches) 147 mm (max) (5.
Installation 3.2 UNPACKING INSTRUCTIONS CAUTION: The maximum limits for physical shock can be exceeded if the drive is not handled properly. Special care should be taken not to bump or drop the drive. It is highly recommended that Quantum Fireball Plus AS drives are not stacked or placed on any hard surface after they are unpacked. Such handling could cause media damage. 1. Open the shipping container and remove the packing assembly that contains the drive. 2. Remove the drive from the packing assembly.
Installation Figure 3-3 Drive Packing Assembly of a Polypropylene 20-Pack Container Note: The 20-pack container should be shipped in the same way it was received from Quantum. When individual drives are shipped from the 20-pack container then it should be appropriately packaged (not supplied with the 20-pack) to prevent damage. Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.
Installation 3.3 HARDWARE OPTIONS The configuration of a Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.0 GB AT hard disk drive depends on the host system in which it is to be installed. This section describes the hardware options that you must take into account prior to installation. Figure 3-4 shows the printed circuit board (PCB) assembly, indicating the jumpers that control some of these options.
Installation The configuration of the following Three jumpers controls the drive’s five modes of operation: • CS – Cable Select • DS – Drive Select • PK– Jumper Parking Position (Slave mode) • AC– Alternate Capacity The AT PCB has two jumper locations provided to configure the drive in a system. The default configuration for the drive as shipped from the factory is with a jumper across the DS location, and open positions in the CS, PK and AC positions.
Installation drive is configured as a Master. If it is a 1 (high), the drive is configured as a Slave. In order to configure two drives in a Master/Slave relationship using the CS jumper, you need to use a cable that provides the proper signal level at pin 28 of the ATA bus connector. This allows two drives to operate in a Master/Slave relationship according to the drive cable placement. The Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.
Installation 3.3.5 Alternate Capacity (AC) For user capacities below 66,055,248 sectors (32 GB), inserting the AC jumper limits the Number of Cylinders field 1 to a value of 16,383, as reported in IDENTIFY DEVICE data word. This allows software drivers to determine that the actual capacity is larger than indicated by the maximum CHS, requiring LBA addressing to use the full capacity.
Installation 3.4 ATA BUS ADAPTER There are two ways you can configure a system to allow the Quantum Fireball Plus AS hard disk drives to communicate over the ATA bus of an IBM or IBMcompatible PC: 1. Connect the drive to a 40-pin ATA bus connector (if available) on the motherboard of the PC. 2. Install an IDE-compatible adapter board in the PC, and connect the drive to the adapter board. 3.4.
Installation 3.5 MOUNTING Drive mounting orientation, clearance, and ventilation requirements are described in the following subsections. 3.5.1 Orientation The mounting holes on the Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.0 GB AT hard disk drives allow the drive to be mounted in any orientation. Figure 3-6 and Figure 3-7 show the location of the three mounting holes on each side of the drive. The drive can also be mounted using the four mounting hole locations on the PCB side of the drive.
Installation Figure 3-8 Mounting Screw Clearance for the Quantum Fireball Plus AS Hard Disk Drives CAUTION: The PCB is very close to the mounting holes. Do not exceed the specified length for the mounting screws. The specified screw length allows full use of the mounting hole threads, while avoiding damaging or placing unwanted stress on the PCB. Figure 3-8 specifies the minimum clearance between the PCB and the screws in the mounting holes.
Installation 3.5.2 Clearance Clearance from the drive to any other surface (except mounting surfaces) must be a minimum of 1.25 mm (0.05 inches). 3.5.3 Ventilation The Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.0 GB AT hard disk drives operate without a cooling fan, provided the ambient air temperature does not exceed 131°F (55°C) at any point along the drive form factor envelope. 3.6 COMBINATION CONNECTOR (J1) J1 is a three-in-one combination connector.
Installation 3.6.1 DC Power (J1, Section A) The recommended mating connectors for the +5 VDC and +12 VDC input power are listed in Table 3-2. Table 3-2 J1 Power Connector, Section A PIN NUMBER VOLTAGE LEVEL MATING CONNECTOR TYPE AND PART NUMBER (OR EQUIVALENT) J1 Section A (4-Pin): 1 +12 VDC 2 Ground Return for +12 VDC 3 Ground Return for +5 VDC 4 +5 VDC Note: 3.6.
Installation 3.7 FOR SYSTEMS WITH A MOTHERBOARD ATA ADAPTER You can install the Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.0 GB AT hard disk drives in an AT-compatible system that contains a 40-pin ATA bus connector on the motherboard. To connect the drive to the motherboard, use a 40 conductor ribbon cable (80 conductor ribbon cable if using Ultra ATA/100 drive) 18 inches in length or shorter. Ensure that pin 1 of the drive is connected to pin 1 of the motherboard connector. 3.
Installation 3.8.1.1 Connecting the Adapter Board and the Drive Use a 40-pin ribbon cable to connect the drive to the board. See Figure 3-10. To connect the drive to the board: 1. Insert the 40-pin cable connector into the mating connector of the adapter board. Make sure that pin 1 of the connector matches with pin 1 on the cable. 2. Insert the other end of the cable into the header on the drive.
Installation Figure 3-11 Completing the Drive Installation 3.9 TECHNIQUES IN DRIVE CONFIGURATION 3.9.1 The 528-Megabytes Barrier Older BIOS that only support Int 13 commands for accessing ATA drives through DOS based operating systems will be limited to use only 1024 cylinders. This will reduce the effective capacity of the drive to 528 Mbytes. Whenever possible the Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.
Installation • Use a hard disk controller that translates the hard drive parameters to an appropriate setup for both MS-DOS and the computer system’s ROM-BIOS. • Insert the Alternate Capacity (AC) jumper on the drive (see Section 3.3.5). 3.9.2 The 8.4-Gigabytes Barrier Newer BIOS’s allow users to configure disk drives to go beyond the 528 MB barrier by using several BIOS translation schemes.
Installation 3.10 SYSTEM STARTUP AND OPERATION Once you have installed the Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.0 GB AT hard disk drive, and adapter board (if required) in the host system, you are ready to partition and format the drive for operation. To set up the drive correctly, follow these steps: 1. Power on the system. 2. Run the SETUP program. This is generally on a Diagnostics or Utilities disk, or within the system’s BIOS.
Installation To match the logical specifications of the drive to the drive type of a particular BIOS, consult the system’s drive-type table. This table specifies the number of cylinders, heads, and sectors for a particular drive type. You must choose a drive type that meets the following requirements: For the 10.2 GB, 20.5 GB, 30.0 GB, 40.0 GB, 60.0 GB: Logical Cylinders x Logical Heads x Logical Sectors/Track x 512 = 8,455,200,768 4.
Chapter 4 SPECIFICATIONS This chapter gives a detailed description of the physical, electrical, and environmental characteristics of the Quantum Fireball Plus AS hard disk drives. 4.1 SPECIFICATION SUMMARY Table 4-1 gives a summary of the Quantum Fireball Plus AS hard disk drives.
Specifications DESCRIPTION Maximum effective areal density (Gb/in2) Performance: Seek times: Read-on-arrival Track-to-track Average write Full stroke Data transfer Rates: Disk to Read Once a Revolution1, 2 Disk to Read Instantaneously1 Read Buffer to ATA Bus (PIO Mode with IORDY) Read Buffer to ATA Bus (Ultra ATA Mode) Buffer Size Reliability: Seek error rate2 Unrecoverable error rate2 Error correction method (with cross check) Projected MTBF3 Contact Start/Stop Cycles3 (Ambient temperature) Auto head-pa
Specifications 4.2 FORMATTED CAPACITY At the factory, the Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.0 GB AT hard disk drives receive a low-level format that creates the actual tracks and sectors on the drive. Table 4-2 shows the capacity resulting from this process. Formatting done at the user level, for operation with DOS, UNIX, or other operating systems, may result in less capacity than the physical capacity shown in Table 4-2. Table 4-2 Formatted Capacity 10.2 GB 20.5 GB 30.0 GB 40.0 GB 60.
Specifications 4.4 TIMING SPECIFICATIONS Table 4-3 illustrates the timing specifications of the Quantum Fireball Plus AS hard disk drives. Table 4-3 Timing Specifications PARAMETER Sequential Cylinder Switch Time3 Sequential Head Switch Time4 Random Average (Read or Seek)9 Random Average (Write)9 Full-Stroke Seek Average Rotational Latency Power On5 to Drive Ready6 Standby7 to Interface Ready Spindown Time, Standby Command Spindown Time, Power loss TYPICAL NOMINAL1 WORST CASE2 0.8 ms 1 ms 8.5 ms 10.
Specifications 4.5 POWER The Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.0 GB AT hard disk drives operate from two supply voltages: • +12V ±10% • +5V ±5% The allowable ripple and noise is 250 mV peak-to-peak for the +12 Volt supply and 150 mV peak-to-peak for the +5 Volt supply. 4.5.1 Power Sequencing You may apply the power in any order, or open either the power or power return line with no loss of data or damage to the disk drive.
Specifications 4.5.3 Power Requirements Table 4-5 lists the voltages and typical average corresponding currents for the various modes of operation of the Quantum Fireball Plus AS hard disk drives. Table 4-5 Typical Power and Current Consumption TYPICAL AVERAGE CURRENT2 (mAmps RMS unless otherwise noted) MODE OF OPERATION MODEL NUMBER +12V 10.2/20.5 GB 30.0/ 40.0GB (1-Disk) (2-Disks) Startup1 (peak) 1775 1800 Idle3 258 Maximum Seeking4 +5V 60.0 GB (3-Disks) 10.2/20.5 GB 30.0/ 40.0GB 60.
Specifications 3. Idle mode is in effect when the drive is not reading, writing, seeking, or executing any commands. A portion of the R/W circuitry is powered down, the motor is up to speed and the Drive Ready condition exists. 4. Maximum seeking is defined as continuous random seek operations with minimum controller delay. 5. Standby mode is defined as when the motor is stopped, the actuator is parked, and all electronics except the interface control are in low power state.
Specifications 4.7 MECHANICAL Quantum Fireball Plus AS hard disk drives are designed to meet the form factor dimensions of the SFF committee specification SFF8300. Height: 26.1 mm maximum Width: 101.6 ± 0.25mm Depth: 147 mm maximum Weight: 1.35 lb 4.8 ENVIRONMENTAL CONDITIONS Table 4-7 summarizes the environmental specifications of the Quantum Fireball Plus AS hard disk drives.
Specifications 4.9 SHOCK AND VIBRATION The Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.0 GB AT hard disk drives can withstand levels of shock and vibration applied to any of its three mutually perpendicular axes, or principal base axis, as specified in Table 4-8. A functioning drive can be subjected to specified operating levels of shock and vibration.
Specifications 4.10 HANDLING THE DRIVE Before handling the Quantum hard disk drive some precautions must to be taken to ensure that the drive is not damaged. Use both hands while handling the drive and hold the drive by its edges. Quantum drives are designed to withstand normal handling, however, hard drives can be damaged by electrostatic discharge (ESD), dropping the drive, rough handling, and mishandling. Use of a properly grounded wrist strap to the earth is strongly recommended.
Specifications 4.12 ELECTROMAGNETIC SUSCEPTIBILITY E Field: 3Volts/meter at <100 MHz. B Field: As per standard EN61004-8 4.13 SPINDLE IMBALANCE 0.5 g-mm maximum (This is approximately equivalent to 0.04 G emitted vibrations) 4.14 DISK ERRORS Table 4-9 provides the error rates for the Quantum Fireball Plus AS hard disk drives.
Chapter 5 BASIC PRINCIPLES OF OPERATION This chapter describes the operation of Quantum Fireball Plus AS AT hard disk drives’ functional subsystems. It is intended as a guide to the operation of the drive, rather than a detailed theory of operation. 5.1 QUANTUM FIREBALL PLUS AS DRIVE MECHANISM This section describes the drive mechanism. Section 5.2 describes the drive electronics. The Quantum Fireball Plus AS hard disk drives consist of a mechanical assembly and a PCB as shown in Figure 5-1.
Basic Principles of Operation Figure 5-1 Quantum Fireball Plus AS AT Hard Disk Drive Exploded View Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.
Basic Principles of Operation 5.1.1 Base Casting Assembly A single-piece, e-coated, aluminum-alloy base casting provides a mounting surface for the drive mechanism and PCB. The base casting also acts as the flange for the DC motor assembly. To provide a contamination-free environment for the HDA, a gasket provides a seal between the base casting, and the metal cover that encloses the drive mechanism. 5.1.
Basic Principles of Operation 5.1.4 Headstack Assembly The headstack assembly consists of read/write heads, head arms, and a coil joined together by insertion molding to form a rotor subassembly, bearings, and a flex circuit. Read/write heads mounted to spring-steel flexures are swage mounted onto the rotary positioner assembly arms. The flex circuit exits the HDA through the base casting. A cover gasket seals the gap. The flex circuit connects the headstack assembly to the PCB.
Basic Principles of Operation 5.1.7 Air Filtration The Quantum Fireball Plus AS AT hard disk drives are Winchester-type drives. The heads fly very close to the media surface. Therefore, it is essential that the air circulating within the drive be kept free of particles. Quantum assembles the drive in a Class-100 purified air environment, then seals the drive with a metal cover. When the drive is in use, the rotation of the disks forces the air inside of the drive through an internal 0.3 micron filter.
Basic Principles of Operation 5.2.1 Integrated µProcessor, Disk Controller and ATA Interface Electronics The µProcessor, Disk Controller, and ATA Interface electronics are contained in a proprietary ASIC developed by Quantum, as shown below in Figure 5-3. Figure 5-3 Block Diagram Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.
Basic Principles of Operation The integrated µProcessor, Disk Controller, and ATA Interface Electronics have nine functional modules (described below): • µProcessor • Digital Synchronous Spoke (DSS) • Error Correction Code (ECC) Control • Formatter • Buffer Controller • Servo Controller, including PWM • Serial Interface • ATA Interface Controller • Motor Controller 5.2.1.1 µProcessor The µProcessor core provides local processor services to the drive electronics under program control.
Basic Principles of Operation 5.2.1.5 Buffer Controller The Buffer Controller supports a 2 MB buffer, which is organized as 1M x 16 bits. The 16-bit width implementation provides a 60 MB/s maximum buffer bandwidth. This increased bandwidth allows the µProcessor to have direct access to the buffer, eliminating the need for a separate µProcessor RAM IC. The Buffer Controller supports both drive and host address rollover and reloading, to allow for buffer segmentation.
Basic Principles of Operation • Clock Synthesizer • PLL • Serial Interface • TA Detection and Correction 5.2.2.1 Pre-Compensator The pre-compensator introduces pre-compensation to the write data received from the sequencer module in the DCIIA. The pre-compensated data is then passed to the R/W Pre-Amplifier and written to the disk. Pre-compensation reduces the write interference from adjacent write bit. 5.2.2.
Basic Principles of Operation 5.2.3 PreAmplifier and Write Driver The PreAmplifier and Write Driver provides write driver and read pre-amplifier functions, and R/W head selection. The write driver receives precompensated write data from the PreCompensator module in the Read/Write ASIC. The write driver then sends this data to the heads in the form of a corresponding alternating current.
Basic Principles of Operation DisCache works by continuing to fill its cache memory with adjacent data after transferring data requested by the host. Unlike a noncaching controller, Quantum’s disk controller continues a read operation after the requested data has been transferred to the host system. This read operation terminates after a programmed amount of subsequent data has been read into the cache segment. The cache memory consists of a 1.
Basic Principles of Operation The requested read data takes up a certain amount of space in the cache segment. Hence, the corresponding prefetch data can essentially occupy the rest of the space within the segment. The other factors determining prefetch size are the maximum and minimum prefetch. The drive’s prefetch algorithm dynamically controls the actual prefetch value based on the current demand, with the consideration of overhead to subsequent commands. 5.3.
Basic Principles of Operation 5.3.2.4 Skew Offsets Table 5-2 Skew Offsets SWITCH TIME WEDGE OFFSET Head Skew 1.75 ms 31 Cylinder Skew 1.20 ms 21 Note: Nominal wedge-to-wedge time of 56.25 ms is used. Worst case instantaneous spindle variation (±0.12%) is used while calculating to provide a safety margin. Wedge offsets are rounded to the closest whole number. 5.3.2.
Basic Principles of Operation The drive does not need to re-read a sector on the next disk revolution or apply ECC for those errors that are corrected on-the-fly. Errors corrected in this manner are invisible to the host system. When errors cannot be corrected on-the-fly, an automatic retry, and a more rigorous 16 10-bit symbols error correction algorithm enables the correction of any sector with single bursts (up to 16 contiguous 10-bit symbols), or up to 16 multiple random one 10-bit symbol burst errors.
Basic Principles of Operation complex firmware ECC algorithm, the drive will always try to recover from an error by attempting to re-read the data correctly. This strategy prevents invoking correction on non-repeatable errors. Each time a sector in error is re-read a set of ECC syndromes is computed. If all of the ECC syndrome values equal zero, and xc syndrome value equals to 0 or 0FF, the data was read with no errors, and the sector is transferred to the host system.
Basic Principles of Operation Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.
Basic Principles of Operation 5-17 Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.
Chapter 6 ATA BUS INTERFACE AND ATA COMMANDS This chapter describes the interface between Quantum Fireball Plus AS 10.2/20.5/ 30.0/40.0/60.0 GB AT hard disk drives and the ATA bus. The commands that are issued from the host to control the drive are listed, as well as the electrical and mechanical characteristics of the interface. 6.1 INTRODUCTION Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.
ATA Bus Interface and ATA Commands Note: Some host systems do not read the Status Register after the drive issues an interrupt. In such cases, the interrupt may not be acknowledged. To overcome this problem, you may have to configure a jumper on the motherboard or adapter board to allow interrupts to be controlled by the drive’s interrupt logic. Read your motherboard or adapter board manual carefully to find out how to do this. 6.4.1.
ATA Bus Interface and ATA Commands Table 6-1 Drive Connector Pin Assignments (J1, Section C) (Continued) SIGNAL NAME DIR PIN DESCRIPTION DD0 17 Bit 0 DD1 15 Bit 1 DD2 13 Bit 2 DD3 11 Bit 3 DD4 9 Bit 4 DD5 7 Bit 5 DD6 5 Bit 6 DD7 3 Bit 7 DD8 4 Bit 8 DD9 6 Bit 9 DD10 8 Bit 10 DD11 10 Bit 11 DD12 12 Bit 12 DD13 14 Bit 13 DD14 16 Bit 14 DD15 18 Bit 15 Ground Ground — 19 Ground between the host system and the drive.
ATA Bus Interface and ATA Commands Table 6-1 Drive Connector Pin Assignments (J1, Section C) (Continued) SIGNAL NAME DIR PIN DESCRIPTION Cable Select — 28 This is a signal from the host that allows the drive to be configured as drive 0 when the signal is 0 (grounded), and as drive 1 when the signal is 1 (high). The drive has a 10kW pull-up resistor on this signal. DMA Acknowledge DACK1– IN 29 Used by the host to respond to the drive’s DMARQ signal.
ATA Bus Interface and ATA Commands Table 6-1 Drive Connector Pin Assignments (J1, Section C) (Continued) SIGNAL Passed Diagnostics NAME PDIAG– DIR I/O PIN 34 DESCRIPTION Drive 0 (Master) monitors this Drive 1 (Slave) opencollector output signal, which indicates the result of a diagnostics command or reset. The drive has a 10K pull-up resistor on this signal. Following the receipt of a power-on reset, software reset, or RESET– drive 1 negates PDIAG– within 1 ms.
ATA Bus Interface and ATA Commands Table 6-1 Drive Connector Pin Assignments (J1, Section C) (Continued) SIGNAL NAME Drive Active/Slave Present DASP– DIR PIN I/O 39 DESCRIPTION A time-multiplexed signal that indicates either drive activity or that drive 1 is present. During power-on initialization, DASP– is asserted by drive 1 within 400 ms to indicate that drive 1 is present. If drive 1 is not present, drive 0 asserts DASP– after 450 ms to light the drive-activity LED.
ATA Bus Interface and ATA Commands 6.4.1.3 Ultra ATA/100 80 Conductor Cable The use of a 80 conductor cable is suggested in order to successfully meet the new Ultra ATA/100 mode 3 and 4 faster timing requirements. The 80 conductor cable is used with the same connector configuration as the standard 40 conductor cable. There is no new signal and the 40 additional lines are ground paths tied together to all 7 original ground conductors.
ATA Bus Interface and ATA Commands Table 6-3 Signal Line Definitions NEW DEFINITION OLD DEFINITION DMARQ = DMARQ –DMACK = –DMACK (These two signals remain unchanged to ensure backward compatibility with PIO modes) –DMARDY = IORDY on WRITE commands = –DIOR on READ commands STROBE = –DIOR on WRITE commands = IORDY on READ commands STOP = –DIOW –CBLID –PDIAG Table 6-4 Interface Signal Name Assignments J1 PIN NUMBER DESCRIPTION HOST DIR DEV ACRONYM 28 CABLE SELECT —> CSEL 37 CHIP SELEC
ATA Bus Interface and ATA Commands J1 PIN NUMBER DESCRIPTION HOST DIR DEV ACRONYM 33 DEVICE ADDRESS BIT 1 —> DA1 36 DEVICE ADDRESS BIT 2 —> DA2 29 DMA ACKNOWLEDGE —> DMACK– 21 DMA REQUEST <— DMARQ 31 INTERRUPT REQUEST <— INTRQ 25 —> I/O READ DMA ready on data in bursts (see note —> —> 2) Data strobe on data out bursts (see note 2) DIOR– HDMARDY– HSTROBE 27 I/O READY <— DMA ready on data out bursts (see <— note 2) <— Data strobe on data in bursts (see note 2) IORDY DDMARDY– DS
ATA Bus Interface and ATA Commands Table 6-5 PIO Host Interface Timing SYMBOL DESCRIPTION t0 Cycle Time QUANTUM Quantum MODE 4 MIN/MAX Fireball Plus (local bus) AS AT 41 min 120 120 t1 Address Valid to DIOW–/DIOR–Setup min 25 25 t2 DIOW–/DIOR– Pulsewidth (8- or 16-bit) min 70 70 t2i DIOW–/DIOR– Negated Pulsewidth min 25 25 t3 DIOW–Data Setup min 20 20 t4 DIOW– Data Hold min 10 10 t5 DIOR– Data Setup min 20 20 t5a DIOR– to Data Valid max — — t6 DIOR– Data Hold m
ATA Bus Interface and ATA Commands 6.4.2.2 Multiword DMA Transfer Mode The multiword DMA host interface timing shown in Table 6-6 is in reference to signals at 0.8 volts and 2.0 volts. All times are in nanoseconds, unless otherwise noted. Figure 6-2 provides a timing diagram.
ATA Bus Interface and ATA Commands Table 6-7 contains the values for the timings for each of the Ultra DMA modes. All timing measurement switching points (low to high and high to low) shall be taken at 1.5V. Table 6-8 contains descriptions and comments for each of the timing values in Table 6-7.
ATA Bus Interface and ATA Commands Notes: 1. All signal transitions for a timing parameter will be measured at the connector specified in the measured location column. For example, in the case of tRFS, both STROBE and DMARDY- transitions are measured at the sender connector. 2. The parameter tLI shall be measured at the connector of the sender or recipient that is responding to an incoming transition from the recipient or sender respectively.
ATA Bus Interface and ATA Commands tZIORDY tACK tSS Minimum time before driving IORDY (see note 4) Setup and hold times for DMACK- (before assertion or negation) Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender terminates a burst) Notes: 1. The parameters tUI, tMLI and tLI indicate sender-to-recipient or recipient-tosender interlocks, i.e., one agent (either sender or recipient) is waiting for the other agent to respond with a signal before proceeding.
ATA Bus Interface and ATA Commands DMARQ (device) Tui DMACK(host) Tack Tenv Tack Tenv STOP (host) HDMARDY(host) Tfs Tfs Tziordy Tdvs DSTROBE (device) Tzad Tzad Taz Tdvh DD(15:0) Tack DA0, DA1, DA2, CS0-, CS1- Figure 6-3 Initiating a Data In Burst T2cyc Tcyc Tcyc T2cyc Tdvs Tdvs DSTROBE at device Tdvh Tdvh Tdvh DD(15:0) at device Tdh Tds Tdh Tds Tdh DSTROBE at host DD(15:0) at host Figure 6-4 Sustained Data In Burst Note: DD(15:0) and DSTROBE signals are shown at both the host and
ATA Bus Interface and ATA Commands DMARQ (device) DMACK(host) Trp STOP (host) Tsr HDMARDY (host) Trfs DSTROBE (device) DD(15:0) (device) Figure 6-5 Host Pausing a Data In Burst Note: The host knows the burst is fully paused Trp ns after HDMARDY- is negated and may then assert STOP to terminate the burst. Tsr timing need not be met for an asynchronous pause.
ATA Bus Interface and ATA Commands Tli DMARQ (device) Tmli Tmli Tdvs DMACK(host) Tack Trp STOP (host) Tack HDMARDY(host) Trfs Tli Tiordyz DSTROBE (device) Tzah Tdvh Taz DD(15:0) CRC Tack DA0, DA1, DA2, CS0-, CS1- Figure 6-7 Host Terminating a Data In Burst DMARQ (device) Tui DMACK(host) Tack Tenv STOP (host) Tziordy Tli Tui DDMARDY(device) Tack Tdvs HSTROBE (host) Tdvh DD(15:0) (host) Tack DA0, DA1, DA2, CS0-, CS1- Figure 6-8 Initiating a Data Out Burst Quantum Fireball Plus AS 10.2/20.
ATA Bus Interface and ATA Commands T2cyc Tcyc Tcyc T2cyc Tdvs Tdvs HSTROBE at host Tdvh Tdvh Tdvh DD(15:0) at host Tds Tdh Tds Tdh Tdh HSTROBE at device DD(15:0) at device Figure 6-9 Sustained Data Out Burst Note: DD(15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until well after they are driven by the host.
ATA Bus Interface and ATA Commands Tli DMARQ (device) Tmli DMACK(host) Tack Tss STOP (host) Tiordyz Tli DDMARDY(device) Tli HSTROBE (host) Tack Tdvs Tdvh DD(15:0) (host) CRC Tack DA0, DA1, DA2, CS0-, CS1- Figure 6-11 Host Terminating a Data Out Burst Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.
ATA Bus Interface and ATA Commands DMARQ (device) Trp Tmli Tmli DMACK(host) Tack Tli STOP (host) Tiordyz DDMARDY(device) Trfs Tli Tack HSTROBE (host) Tdvs Tdvh DD(15:0) (host) CRC Tack DA0, DA1, DA2, CS0-, CS1- Figure 6-12 Device Terminating a Data out Burst 6.4.2.3 Host Interface RESET Timing The host interface RESET timing shown in Table 6-9 is in reference to signals at 0.8 volts and 2.0 volts. All times are in nanoseconds, unless otherwise noted. Figure 613 provides a timing diagram.
ATA Bus Interface and ATA Commands 6.5 REGISTER ADDRESS DECODING The host addresses the drive by using programmed I/O. Host address lines A0–A2, chip-select CS1FX– and CS3FX–, and IOR– and IOW– address the disk registers. Host address lines A3–A9 generate the two chip-select signals, CS1FX– and CS3FX–. • Chip Select CS1FX– accesses the eight Command Block Registers. • Chip Select CS3FX– is valid during 8-bit transfers to or from the Alternate Status Register.
ATA Bus Interface and ATA Commands FUNCTION Drive/Head4 LBA Bits 24–275 HOST SIGNALS Drive/Head A N 1 1 0 LBA Bits 24–27 A N 1 1 0 Status Command A N 1 1 1 Invalid Address Invalid Address A A X X X 1. N = signal deasserted 2. X = signal either asserted or deasserted 3. A = signal asserted 4. Mapping of registers in CHS mode 5.
ATA Bus Interface and ATA Commands 6.6.1.2 Device Control Register This write-only register contains two control bits, as shown in Table 6-12. Table 6-12 Device Control Register Bits BIT MNEMONIC DESCRIPTION 7 Reserved – 6 Reserved – 5 Reserved – 4 Reserved – 3 1 Always 1 2 SRST1 Host software reset bit 1 nIEN2 Drive interrupt enable bit 0 0 Always 0 1. SRST = Host Software Reset bit. When the host sets this bit, the drive is reset.
ATA Bus Interface and ATA Commands 6.6.1.3 Drive Address Register The Drive Address Register returns the head-select addresses for the drive currently selected. Table 6-13 shows the Drive Address bits. Table 6-13 Drive Address Register Bits BIT MNEMONIC 7 HiZ1 6 nWTG2 DESCRIPTION High Impedance bit 3 Write Gate bit Head Address msb 5 nHS3 4 nHS2 3 nHS1 – 2 nHS0 Head Address lsb 1 nDS14 Drive 1 Select bit 0 nDS0 Drive 0 Select bit – 1. HiZ = High Impedance bit.
ATA Bus Interface and ATA Commands Table 6-14 Error Register Bits MNEMONIC BIT # 7 # 6 # 5 # 4 # 3 ABRT 2 # 1 # 0 6.6.2.3 DESCRIPTION Requested command aborted due to a drive status error, such as Not Ready or Write Fault, or because the command code is invalid. Sector Count Register The Sector Count Register defines the number of sectors of data to be transferred across the host bus for a subsequent command. If the value in this register is 0, the sector count is 256 sectors.
ATA Bus Interface and ATA Commands 6.6.2.6 Cylinder High Register The Cylinder High Register contains the eight high-order bits of the starting cylinder address for any disk access. On multiple sector transfers that cross cylinder boundaries, the drive updates this register at the completion of command execution, to reflect the current cylinder number. The host loads the most significant bits of the cylinder address into the Cylinder High Register. In LBA mode, this register contains bits 16 to 23.
ATA Bus Interface and ATA Commands 6.6.2.8 Status Register The Status Register contains information about the status of the drive and the controller. The drive updates the contents of this register at the completion of each command. When the Busy bit is set (BSY=1), no other bits in the Command Block Registers are valid. When the Busy bit is not set (BSY=0), the information in the Status Register and Command Block Registers is valid.
ATA Bus Interface and ATA Commands 6.6.2.9 Command Register The host sends a command to the drive by means of an 8-bit code written to the Command Register. As soon as the drive receives the command in its Command Register, it begins execution of the command. Table 6-17 lists the hexadecimal command codes and parameters for each executable command. The code F0h is common to all of the extended commands. Each of these commands is distinguished by a unique subcode.
ATA Bus Interface and ATA Commands SC = Sector Count Register SN = Sector Number Register CY = Cylinder Low and High Registers DS = Drive Select bit (Bit 4 of Drive/Head Register) HD = 4 Head Select Bits (Bits 0–3 of Drive Head Register) V = Must contain valid information for this command Head FR = Features Register 6.7 COMMAND DESCRIPTIONS The Quantum Fireball Plus AS hard disk drives support all standard ATA drive commands.
ATA Bus Interface and ATA Commands ERROR OUTPUTS Register 7 Error na Sector Count na Sector Number na Cylinder Low na 6 5 4 3 na na na na 2 ABRT 1 TK0NF 0 na Cylinder High Device/ Head obs na obs DEV HEAD number or LBA Status BSY DRDY na na DRQ 6.7.2 na na ERR Read Sectors COMMAND CODE – 20h DESCRIPTION – The READ sectors command reads from 1 to 256 sectors, beginning at the specified sector.
ATA Bus Interface and ATA Commands 6.7.3 Write Sectors COMMAND CODE – 30h DESCRIPTION – The WRITE sectors command reads from 1 to 256 sectors, beginning at the specified sector. As specified in the command block register, a sector count equal to 0 requests 256 sectors. When the drive accepts this command, it sets DRQ and waits for the host to fill the sector buffer with data to be written to the drive. The drive does not generate an interrupt to start the first buffer-fill operation.
ATA Bus Interface and ATA Commands 6.7.4 Read Verify Sectors COMMAND CODE – 40h DESCRIPTION – The READ VERIFY sectors executes similarly to the READ SECTORS command but without ever generating an interrupt (DRQ) so that no data is transferred to the host.
ATA Bus Interface and ATA Commands 6.7.5 Seek COMMAND CODE – 70h DESCRIPTION – The SEEK command causes the actuator to seek to the LBA or Cylinder location indicated in the LBA Registers or Cylinder Registers. When the drive receives this command in its Command Block Registers, it performs the following functions: 1. Sets BSY 2. Initiates the seek operation 3. Resets BSY 4.
ATA Bus Interface and ATA Commands 6.7.6 Execute Drive Diagnostics COMMAND CODE – 90h DESCRIPTION – The EXECUTE DRIVE DIAGNOSTIC command performs the internal diagnostics test implemented in the drive. Drive 0 sets BSY within 400 ns of receiving the command. If drive 1 is present: • Both drives execute diagnostics. • Drive 0 waits up to six seconds for drive 1 to assert PDIAG-. • If drive 1 does not assert PDIAG- to indicate a failure, drive 0 appends 80h with its own diagnostics status.
ATA Bus Interface and ATA Commands INPUTS Register 7 6 5 Features na Sector Count Sector count Sector Number Sector Number or LBA Cylinder Low Cylinder low or LBA Cylinder High Cylinder high or LBA Device/ Head obs Command 90h 4 LBA obs DEV 6 5 4 3 na 2 1 0 Head Number or LBA OUTPUTS Register 7 Error Diagnostic Code Sector Count Signature Sector Number Signature Cylinder Low Signature Cylinder High Signature Device/ Head Signature Status BSY DRDY DF na 3 D
ATA Bus Interface and ATA Commands 6.7.7 INITIALIZE DRIVE PARAMETERS COMMAND CODE – 91h DESCRIPTION – The INITIALIZE DRIVE PARAMETERS command enables the host to set the logical number of heads and the logical number of sectors per track. On receiving the command, the drive sets the BSY bit, saves the parameters, clears the BSY, and generates an interrupt.
ATA Bus Interface and ATA Commands 6.7.8 Download Microcode COMMAND CODE - 92h TYPE - Optional PROTOCOL - PIO data out INPUTS - The head bits of the device/head register will always be set to zero. The cylinder high and low registers will be set to zero. The sector number and the sector count are used together as a 16-bit sector count value. The feature register specifies the subcommand code.
ATA Bus Interface and ATA Commands Sector Count register will indicate no data is to transferred. This allows transfer sizes from 0 bytes to 33, 553, 920 bytes in 512 byte increments. The Features register will be used to determine the effect of the DOWNLOAD MICROCODE sub command. The values for the Feature Register are: 01h — download is for immediate, temporary use 07h — save downloaded code for immediate and future use. Either or both values may be supported. All other values are reserved. 6.7.
ATA Bus Interface and ATA Commands PREREQUISITES - DRDY set equal to one. SMART enabled. DESCRIPTION - This command disables all SMART capabilities within the device including any and all timer functions related exclusively to this feature. After receipt of this command the device will disable all SMART operations. Attribute values will no longer be monitored or saved by the device. The state of SMART (either enabled or disabled) will be preserved by the device across power cycles.
ATA Bus Interface and ATA Commands NORMAL OUTPUTS - None ERROR OUTPUTS - If the device does not support this command, if SMART is disabled or if the values in the Features, Cylinder Low or Cylinder High registers are invalid, an Aborted command error is posted.
ATA Bus Interface and ATA Commands 6.7.9.2 SMART ENABLE OPERATIONS COMMAND CODE - B0h TYPE - Optional - SMART Feature set. If the SMART feature set is implemented, this command shall be implemented. PROTOCOL - Non-data command INPUTS - The Features register shall be set to D8h. The Cylinder Low register shall be set to 4Fh. The Cylinder High register shall be set to C2h.
ATA Bus Interface and ATA Commands 6.7.9.3 SMART READ ATTRIBUTE THRESHOLDS COMMAND CODE - B0h TYPE - Optional - SMART Feature set. If the SMART feature set is implemented, this command is optional and not recommended. PROTOCOL - PIO data in INPUTS - The Features register shall be set to D1h. The Cylinder Low register shall be set to 4Fh. The Cylinder High register shall be set to C2h.
ATA Bus Interface and ATA Commands Table 6-19 defines the twelve bytes that make up the information for each threshold entry in the device attribute thresholds data structure. Attribute entries in the individual threshold data structure must be in the same order and correspond to the entries in the individual attribute data structure. The attribute ID numbers are vendor specific. Any non-zero value in the attribute ID number indicates an active attribute.
ATA Bus Interface and ATA Commands Table 6-21 Device SMART Data Structure Byte Description 0-361 Vendor Specific 362 Off-line data collection Status 363 Vendor specific 364-365 Total time in seconds to complete off-line data collection 366 Vendor Specific 367 Off-line data collection capability 368-369 SMART capability 370-385 Reserved 386-510 Vendor Specific 511 Data Structure check sum The attribute ID numbers and their definitions are vendor specific.
ATA Bus Interface and ATA Commands 6.7.9.4 SMART RETURN STATUS COMMAND CODE - B0h TYPE - Optional - SMART Feature set. If the SMART feature set is implemented, this command shall be implemented. PROTOCOL - Non-data command. INPUTS - The Features register shall be set to DAh. The Cylinder Low register shall be set to 4Fh. The Cylinder High register shall be set to C2h.
ATA Bus Interface and ATA Commands 6.7.9.5 SMART SAVE ATTRIBUTE VALUES COMMAND CODE - B0h TYPE - Optional - SMART Feature set. If the SMART feature set is implemented, this command is optional and not recommended. PROTOCOL - Non-data command INPUTS - The Features register shall be set to D3h. The Cylinder Low register shall be set to 4Fh. The Cylinder High register shall be set to C2h.
ATA Bus Interface and ATA Commands 6.7.9.6 SMART EXECUTE OFF-LINE COLLECTION IMMEDIATE COMMAND CODE - B0h PROTOCOL - Non-data command INPUTS - The Features register shall be set to D4h. The Cylinder Low register shall be set to 4Fh. The Cylinder High register shall be set to C2h.
ATA Bus Interface and ATA Commands PREREQUISITES - DRDY set equal to one. SMART enabled. DESCRIPTION - Upon issuing of the SMART command sub-code D4 the drive will begin an off-line testing. Any ECC correctable errors encountered during the off-line testing of the drive are counted, and upon completion the attribute list is updated accordingly. Shown below are the off-line data collection status byte values.
ATA Bus Interface and ATA Commands ERROR OUTPUTS Register 7 6 Error na Sector Count na Sector Number Sector Number or LBA Cylinder Low Cylinder low or LBA Cylinder High Cylinder high or LBA Device/ Head obs Na Status BSY DRDY 6.7.
ATA Bus Interface and ATA Commands 6.7.12 Set Multiple Mode COMMAND CODE – C6h The SET MULTIPLE MODE command enables the controller to perform READ MULTIPLE and WRITE MULTIPLE operations, and establishes the block count for these commands. Prior to issuing a command, the host should load the Sector Count Register with the number of sectors per block. On receiving this command, the drive sets BSY and checks the contents of the Sector Count Register.
ATA Bus Interface and ATA Commands 6.7.13 Read DMA COMMAND CODE – C8h;C9h DESCRIPTION – The READ DMA command allows the host to write data using the DMA transfer protocol.
ATA Bus Interface and ATA Commands 6.7.14 Write DMA COMMAND CODE – CAh,CBh DESCRIPTION – The Write DMA command allows the host to write data using the DMA transfer protocol. The host should not use the CBh value.
ATA Bus Interface and ATA Commands 6.7.14.1 Power Management Commands The Quantum Fireball Plus AS hard disk drive provides numerous power management options. Two important options center around a count down counter known as the automatic power down counter or APD. This counter can trigger one of two power saving events depending on which of the two commands was most recently issued. • Standby: Once a standby command is issued, the drive enters the standby mode.
ATA Bus Interface and ATA Commands 6.7.15 STANDBY IMMEDIATE COMMAND CODE – E0h DESCRIPTION – The STANDBY IMMEDIATE power command immediately puts the drive in the standby mode. Power is removed from the spindle motor (the drive’s PCB power is on) and the heads are parked.
ATA Bus Interface and ATA Commands 6.7.16 IDLE IMMEDIATE COMMAND CODE – E1h DESCRIPTION – The IDLE IMMEDIATE command immediately puts the drive in the IDLE mode.
ATA Bus Interface and ATA Commands 6.7.17 STANDBY COMMAND CODE – E2h DESCRIPTION – The STANDBY command causes the drive to enter the STANDBY mode. If the Sector Count register is non-zero then the standby timer will be enabled.
ATA Bus Interface and ATA Commands 6.7.18 IDLE COMMAND CODE – E3h DESCRIPTION – The IDLE command immediately puts the drive into IDLE mode. The sector count register is examined. If the value of the register is not zero, the auto-power down feature is enabled and takes effect once the countdown timer reaches zero. The valid countdown range is listed in Table 6-22.
ATA Bus Interface and ATA Commands 6.7.19 READ BUFFER COMMAND CODE – E4h DESCRIPTION – The READ BUFFER command enables the host to read the current contents of the drive's sector buffer. When the host issues this command, the drive sets BSY, sets up the sector buffer for a read operation, sets DRQ, clears BSY, and generates an interrupt. The host then reads up to 512 bytes of data from the buffer.
ATA Bus Interface and ATA Commands 6.7.20 CHECK POWER MODE COMMAND CODE – E5h DESCRIPTION – The CHECK POWER MODE allows the HOST to probe the drive to determine its current power mode status.
ATA Bus Interface and ATA Commands 6.7.21 SLEEP COMMAND CODE – E6h DESCRIPTION – The Quantum Quantum Fireball Plus AS hard disk drives considers the SLEEP Mode to be equivalent to the STANDBY mode, except that a hardware reset or a software reset is required before issuing any command to the drive.
ATA Bus Interface and ATA Commands 6.7.22 FLUSH CACHE COMMAND CODE – E7h DESCRIPTION – The FLUSH CACHE command allows the HOST to request the device to flush (empty) the write cache. When the host issues this command, the drives sets BSY and proceeds to write all the cached data to the media.
ATA Bus Interface and ATA Commands 6.7.23 WRITE BUFFER COMMAND CODE – E8h DESCRIPTION – The WRITE BUFFER command enables the host to write to the drive's sector buffer. When the host issues this command, the drive sets BSY, sets up the sector buffer for a write operation, sets DRQ, clears BSY, and generates an interrupt. The host then writes up to 512 bytes of data to the buffer.
ATA Bus Interface and ATA Commands 6.7.24 IDENTIFY DRIVE COMMAND CODE – ECh DESCRIPTION – The IDENTIFY DRIVE command allows the host to receive parameter information from the drive. When the host issues this command, the drives sets BSY, stores the required parameter information on the sector buffer, sets DRQ, and generates an interrupt. The host then reads the information from the sector buffer. The identify drive parameters, shown in Table 6-24, defines the parameter words stored in the buffer.
ATA Bus Interface and ATA Commands INPUTS Register 7 Features na Sector Count na Sector Number na Cylinder Low na Cylinder High na Device/ Head obs Command ECh 6 na 5 4 obs DEV 5 4 3 2 1 0 3 2 1 0 na OUTPUTS Register 7 Error na Sector Count na Sector Number na Cylinder Low na Cylinder High na Device/ Head Status 6 na na na na ABRT na na obs na obs DEV na na na na BSY DRDY DF na DRQ na na ERR 6-64 Quantum Fireball Plus AS 10.2/20.5/30.
ATA Bus Interface and ATA Commands Table 6-24 Identify Drive Parameters WORDS1 PARAMETER DESCRIPTION WORD BIT BIT VALUE 0 15 0 0 = ATA device 14 0 Retired 13 0 12 0 11 0 10 1 9 0 8 0 7 0 1 = Removable media 6 1 1 = Not removable controller and/or device 5 0 Retired 4 1 3 1 2 0 1 1 0 0 1 2 3 10.2AT = 16,383 20.5AT = 16,383 30.0AT = 16,383 40.0AT = 16,383 60.
ATA Bus Interface and ATA Commands WORDS1 WORD BIT BIT VALUE 21 374h 22 4 23–26 27–46 47 15–8 7–0 48 49 51 52 53 Buffer size in 512-byte increments Number of ECC bytes passed on READ/WRITE LONG commands Firmware revision (8 ASCII characters) QUANTUM FIREBALL Model number (40 ASCII characters) P AS 10.2A QUANTUM FIREBALL P AS 20.5A QUANTUM FIREBALL P AS 30.0A QUANTUM FIREBALL P AS 40.0A QUANTUM FIREBALL P AS 60.
ATA Bus Interface and ATA Commands WORDS1 WORD 60–61 62 63 BIT BIT VALUE PARAMETER DESCRIPTION (Statements below are true if the bit is set to 1) 10.2AT = 20,066,251 20.5AT = 40,132,503 Total number of User Addressable Sectors 30.0AT = 58,633,344 (LBA Mode only) 40.0AT = 78,177,792 60.
ATA Bus Interface and ATA Commands WORDS1 WORD BIT 83 (Statements below are true if the bit is set to 1) 4101h Command sets supported. If words 82 and 83 =0000h or FFFFh command set notification is not supported.
ATA Bus Interface and ATA Commands WORDS1 WORD BIT BIT VALUE 86 15–10 1h 9 8 7 6 5 4 3 2 1 0 87 88 4000h 15 14 13–0 15–14 13 12 11 10 9 8 93 94 7–6 5 4 3 2 1 0 15–14 13 0-12 15–8 7-0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 PARAMETER DESCRIPTION (Statements below are true if the bit is set to 1) Command set/feature enabled. If words 85, 86, and 87 = 0000h or FFFFh command set enabled notification is not supported.
ATA Bus Interface and ATA Commands 2. The serial number has the following format: 00QTMTCYJJJLSSSSBBB where:00 = Placeholders QT = Quantum M = Place of manufacture T = Drive type family (fixed at 2) C = Drive capacity Y = Last digit of year drive built JJJ = Julian date L = Manufacturing production line SSSS = Sequence of manufacture BBB = Blanks (placeholders) 3. n is a variable from zero to 16. 4. Model Numbers are byte swapped for readability. See Note 1. 6-70 Quantum Fireball Plus AS 10.2/20.5/30.
ATA Bus Interface and ATA Commands 6.7.
ATA Bus Interface and ATA Commands 6.7.27 Read Defect List The READ DEFECT LIST command enables the host to retrieve the drive’s defect list. Prior to issuing the Read Defect List command the host should issue the Read Defect List Length command. This command will not transfer any data. It instead, stores the length in sectors of the defect list in the Sector Count register (1F2), and the Sector Number register (1F3), with the Sector Count register containing the LSB of the 2-byte value (see Table 6-26).
ATA Bus Interface and ATA Commands Table 6-27 AT READ DEFECT LIST Command Bytes ADDRESS 1F2 VALUE Length in Sectors (LSB) DEFINITION Defect List Subcode 1F3 Length in Sectors (MSB) Defect List Subcode 1F4 FFh Password 1F5 3Fh Password 1F6 AXh = Drive 0 Drive Select BXh = Drive 1 — 1F7 F0h Extended Command Code Note: Registers 1F2h and 1F3h must contain the transfer length that is appropriate for the specific product, and 1F4h and 1F5h must contain the exact values shown.
ATA Bus Interface and ATA Commands Table 6-28 DEFECT LIST DATA FORMAT BYTE 0 1 2 3 4–11 12–19 DESCRIPTION 0 1Dh 8* (Number of Defects) (MSB) 8* (Number of Defects) (LSB) Defect Entry #1 Defect Entry #2 • • Table 6-29 DEFECT ENTRY DATA FORMAT BYTE 0 1 2 3 4 5 6 7 DESCRIPTION Defect cylinder (MSB) Defect cylinder Defect cylinder (LSB) Defect head Defect sector (MSB) Defect sector Defect sector Defect sector (LSB) Note: Bytes 4 – 7 will be set to FFh for bad track entries.
ATA Bus Interface and ATA Commands 6.7.28 Configuration In addition to the SET FEATURES command, the Quantum Fireball Plus AS 10.2/ 20.5/30.0/40.0/60.0 GB AT hard disk drives provide two configuration commands: • The SET CONFIGURATION command, which enables the host to change DisCache and Error Recovery parameters • The READ CONFIGURATION command, which enables the host to read the current configuration status of the drive See Chapter 5 for more details about DisCache and setting cache parameters.
ATA Bus Interface and ATA Commands in Table 6-31. However, in the READ CONFIGURATION command, bytes 0 through 31 of the data field are not KEY information, as they are in the SET CONFIGURATION command. The drive reads these bytes as QUANTUM CONFIGURATION, followed by eleven spaces. Users can read the configuration into a buffer, then alter the configuration parameter settings. 6.7.28.2 Set Configuration – FEh/FFh The SET CONFIGURATION command is secured to prevent accessing it accidentally.
ATA Bus Interface and ATA Commands Table 6-32 Accessing the SET CONFIGURATION WITHOUT SAVING TO DISK Command ADDRESS VALUE DEFINITION 1F2h FEh Set Configuration Subcode 1F3h FFh Password 1F4h FFh Password 1F5h 3Fh Password 1F6h AXh (Drive 0) Drive Select BXh Drive 1) Drive Select F0h Extended Command Code 1F7h Note: In Table 6-32: Registers 1F2h through 1F5h must contain the exact values shown above. These values function as a key.
ATA Bus Interface and ATA Commands Table 6-33 Configuration Command Format BYTE BIT 7 6 5 4 0–31 QUANTUM CONFIGURATION KEY 32 RESERVED = 0 33 RESERVED 34 RESERVED = 0 35 RESERVED = 0 36 AWRE 37 NUMBER OF RETRIES 38 ECC CORRECTION SPAN 39 RESERVED = 0 40–511 RESERVED = 0 ARR N/A RC 3 EEC 2 1 0 PE CE N/A N/A DCR WCE RUEE 0 Note: All fields marked RESERVED or N/A should be set to zero. 6.7.28.
ATA Bus Interface and ATA Commands RC – Read Continuous (Byte 36, Bit 4): When set to 1, this bit instructs the drive to transfer data of the requested length without adding delays to increase data integrity—that is, delays caused by the drive’s error-recovery procedures. With RC set to 1 to maintain a continuous flow of data and avoid delays, the drive may send data that is erroneous. When the drive ignores an error, it does not post the error.
ATA Bus Interface and ATA Commands 6.7.29.1 Read Native Max Address. Feature Set: Host Protected Area This command return the native maximum address. The native maximum address is the highest address accepted by the device in the factory default condition. The native maximum address is the maximum address that is valid when using the SET MAX ADDRESS command.
ATA Bus Interface and ATA Commands SET MAX ADDRESS Inputs Register 7 6 5 4 3 Features 00h Sector Count na Sector Number Native max address sector number or set max LBA Cylinder Low Set max cylinder low or LBA 2 1 0 VV Cylinder High Set max cylinder high or LBA Device/Head obs Command F9h LBA obs DEV Native max address head number or set max LBA Features - will be equal to 00h. Sector Count - VV (Value Volatile).
ATA Bus Interface and ATA Commands Cylinder High - Maximum cylinder number high or LBA bits (23:16) set on the device. Device/Head - DEV will indicate the selected device. Maximum native head number or LBA bits (27:24) set on the device. Description After successful command completion all read and write access attempts to addresses greater than specified by the successful SET MAX ADDRESS command will be rejected with an IDNF error.
ATA Bus Interface and ATA Commands Description This command requests a transfer of a single sector of data from the host. The Table below defines the content of this sector of information. The password is retained by the device until the next power cycle. When the device accepts this command the device is in Set_Max_Unlocked state. WORD 0 CONTENT Reserved 1 - 16 Password (32 bytes) 17 - 255 Reserved SET MAX LOCK Command Code F9h with the content of the Features register equal to 02h.
ATA Bus Interface and ATA Commands SET MAX UNLOCK Command Code F9h with the content of the Features register equal to 03h. Inputs Register 7 Features 03h Sector Count na Sector Number na Cylinder Low na Cylinder High na Device/Head obs Command F9h 6 na 5 obs 4 DEV 3 2 1 0 na Description This command requests a transfer of a single sector of data from the host. The Table below defines the content of this sector of information.
ATA Bus Interface and ATA Commands SET MAX FREEZE LOCK Command Code F9h with the content of the Features register equal to 04h. Inputs Register 7 Features 04h Sector Count na Sector Number na Cylinder Low na Cylinder High na Device/Head obs Command F9h 6 na 5 obs 4 DEV 3 2 1 0 na Description The SET MAX FREEZE LOCK command sets the device to Set_Max_Frozen state. After command completion any subsequent SET MAX commands are rejected.
ATA Bus Interface and ATA Commands 6.8 ERROR REPORTING At the start of a command’s execution, the Quantum Fireball Plus AS 10.2/20.5/ 30.0/40.0/60.0 GB AT hard disk drives check the Command Register for any conditions that would lead to an abort command error. The drive then attempts execution of the command. Any new error causes execution of the command to terminate at the point at which it occurred. Table 6-34 lists the valid errors for each command.
ATA Bus Interface and ATA Commands DRDY=Drive ready DSC=Disk seek complete not detected DF=Device fault detected ERR=Error bit in the Status Register IDNF=Requested ID not found TK0=Track zero not found error UNC=Uncorrectable data error Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.
ATA Bus Interface and ATA Commands 6-88 Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.
GLOSSARY A ACCESS – (v) Read, write, or update information on some storage medium, such as a disk. (n) One of these operations. ACCESS TIME – The interval between the time a request for data is made by the system and the time the data is available from the drive. Access time includes the actual seek time, rotational latency, and command processing overhead time. See also seek, rotational latency, and overhead. ACTUATOR – Also known as the positioner.
Glossary BPI – Abbreviation for bits per inch. A measure of how densely information is packed on a storage medium. Flux changes per inch is also a term commonly used in describing storage density on a magnetic surface. BUFFER – An area of RAM reserved for temporary storage of data that is waiting to be sent to a device that is not yet ready to receive it. The data is usually on its way to or from the disk drive or some other peripheral device.
Glossary DISK CONTROLLER – A plug-in board, or embedded circuitry on the drive, that passes information to and from the disk. The Quantum disk drives all have controllers embedded on the drive printed-circuit board. DISKWARE – The program instructions and data stored on the disk for use by a processor. DMA – Acronym for direct memory access.
Glossary G GIGABYTE (GB) – One billion bytes (one thousand megabytes). GUIDE RAILS – Plastic strips attached to the sides of a disk drive mounted in an IBM AT and compatible computers so that the drive easily slides into place. H HALF HEIGHT – Term used to describe a drive that occupies half the vertical space of the original full size 5 1/4-inch drive. 1.625 inches high.
Glossary K M KILOBYTE (K) – A unit of measure consisting of 1,024 (210) bytes. L LANDING ZONE – A position inside the disk’s inner cylinder in a non data area reserved as a place to rest the heads during the time that power is off. Using this area prevents the heads from touching the surface in data areas upon power down, adding to the data integrity and reliability of the disk drive. MB – See megabyte.
Glossary MTTR – Mean Time To Repair. The average time it takes to repair a drive that has failed for some reason. This only takes into consideration the changing of the major sub-assemblies such as circuit board or sealed housing. Component level repair is not included in this number as this type of repair is not performed in the field. O to provide more data storage surfaces in a small package. The platter is coated with a magnetic material that is used to store data as transitions of magnetic polarity.
Glossary RLL – Run Length Limited. A method used on some hard disks to encode data into magnetic pulses. RLL requires more processing, but stores almost 50% more data per disk than the MFM method. SETTLE TIME – The interval between when a track to track movement of the head stops, and when the residual vibration and movement dies down to a level sufficient for reliable reading or writing. ROM – Acronym for read only memory.
Glossary T THIN FILM – A type of coating, used for disk surfaces. Thin film surfaces allow more bits to be stored per disk. TPI – Acronym for tracks per inch. The number of tracks or cylinders that are written in each inch of travel across the surface of a disk. TRACK – One of the many concentric magnetic circle patterns written on a disk surface as a guide to where to store and read the data. TRACK DENSITY – How closely the tracks are packed on a disk surface.
INDEX A abbreviations 1-1 actuator lock 5-4 adapter board 2-7, 3-13, 6-1 Adaptive Caching 5-10 Adaptive segmentation 5-10 air filtration 5-5 AIRLOCK® 5-4 alternate status register 6-22 ARR (automatic read reallocation) 6-78 ARRE bit 5-15 AWRE (automatic write reallocation enabled) 6-78 B base casting 5-3 BIOS 6-1 bits, status register 6-27 block diagram 5-5 Buffer Controller 5-8 busy bit 6-27 C Cable Select 3-6 cable select (CS) jumper 3-5 CE (cache enable) 6-78 check bytes 5-14 clean room 5-1 clearance 3
Index ECC error handling 5-14 EEC (enable early correction) 6-79 ENDEC 5-7 error bit 6-27 error detection, correction 5-13 error rates 5-13 error recovery parameters 6-78 error register 6-24 error reporting 6-86 F faceplate 3-1 firmware features 5-10 flex circuit.
Index Q T Quantum configuration key 6-78 tampering with the HDA 5-1 temperature 4-4 theory of operation 5-1 timebase generator 5-9 timing diagram 6-9, 6-11, 6-20 transient voltages 4-5 TTL logic 6-2 R R/W head matrix 5-10 RC (read continuous) 6-79 read configuration 6-75 read defect list 6-72 read preamplifier 5-4 read/write ASIC 5-10 register error 6-24 reset 6-23 Reset Limits 4-5 ripple 4-5 rotary positioner 5-4 rotary positioner assembly 5-4 RUEE (reallocate uncorrectable error enables) 6-79 U UNIX
Index I-4 Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.
