Specifications

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50 100 150 200 250 300

OIP3 (dBm)

FILTER INPUT RESISTANCE ()

POWER GAIN (dB)

f = 200 MHz

OUT

= 2V

PPD

@ filter input

LMH6522

www.ti.com

SNOSB53D –JULY 2011–REVISED MARCH 2013

LMH6522 High Performance Quad DVGA

Check for Samples: LMH6522

Each channel of LMH6522 has an independent,

FEATURES

digitally controlled attenuator and a high linearity,

• OIP3: 49dBm @ 200MHz

differential output, amplifier. All circuitry has been

• Noise Figure: 8.5dB

optimized for low distortion and maximum system

design flexibility. Power consumption is managed by

• Voltage Gain: 26dB

a three-state enable pin. Individual channels can be

• 1dB Gain Steps

disabled or placed into a Low Power Mode or a

• −3dB Bandwidth of 1400 MHz

higher performance, High Power Mode.

• Gain Step Accuracy: 0.2 dB

The LMH6522 digitally controlled attenuator provides

• Disable Function for Each Channel

precise 1dB gain steps over a 31dB range. The digital

attenuator can be controlled by either a SPI™ Serial

• Parallel and Serial Gain Control

bus or a high speed parallel bus.

• Low Power Mode for Power Management

The output amplifier has a differential output, allowing

Flexibility

large signal swings on a single 5V supply. The low

• Small Footprint WQFN Package

impedance output provides maximum flexibility when

driving a wide range filter designs or analog to digital

APPLICATIONS

converters. For applications which have very large

• Cellular Base Stations changes in signal level LMH6522 can support up to

62dB of gain range by cascading channels.

• Wideband and Narrowband IF Sampling

Receivers

The LMH6522 operates over the industrial

temperature range of −40°C to +85°C. The LMH6522

• Wideband Direct Conversion

is available in a 54-Pin, thermally enhanced, WQFN

• ADC Driver

package.

DESCRIPTION

Performance Curve

The LMH6522 contains four, high performance,

digitally controlled variable gain amplifiers (DVGA). It

has been designed for use in narrowband and

broadband IF sampling applications. Typically, the

LMH6522 drives a high performance ADC in a broad

range of mixed signal and digital communication

applications such as mobile radio and cellular base

stations where automatic gain control (AGC) is

required to increase system dynamic range.

Figure 1. OIP3 vs Filter Input Resistance

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SPI is a trademark of Motorola, Inc..

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (34 pages)

PAGE 1
LMH6522 www.ti.com SNOSB53D – JULY 2011 – REVISED MARCH 2013 LMH6522 High Performance Quad DVGA Check for Samples: LMH6522 • OIP3: 49dBm @ 200MHz Noise Figure: 8.5dB Voltage Gain: 26dB 1dB Gain Steps −3dB Bandwidth of 1400 MHz Gain Step Accuracy: 0.
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LMH6522 SNOSB53D – JULY 2011 – REVISED MARCH 2013 www.ti.com Block Diagram +5V Attenuator INA+ OUTA+ 26 dB INA- OUTA- 0 dB to 31 dB Attenuator INB+ OUTB+ 26 dB INB- ATTEN_A 5 5 EN_A 4 SPI ATTEN_D OUTB- 0 dB to 31 dB 5 Digital Control, (Serial or Parallel) EN_B MODE 5 EN_D INC+ ATTEN_B ATTEN_C EN_C Attenuator OUTC+ 26 dB INC- IND+ OUTC- 0 dB to 31 dB Attenuator OUTD+ 26 dB IND- 0 dB to 31 dB OUTD- GND These devices have limited built-in ESD protection.
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LMH6522 www.ti.com SNOSB53D – JULY 2011 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) ESD Tolerance (3) Human Body Model 2 kV Machine Model 200V Charged Device Model 750V −0.6V to 5.5V Positive Supply Voltage (Pin 3) Differential Voltage between Any Two Grounds <200 mV Analog Input Voltage Range −0.6V to 5.5V Digital Input Voltage Range −0.6V to 5.
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LMH6522 SNOSB53D – JULY 2011 – REVISED MARCH 2013 www.ti.com 5V Electrical Characteristics (1) (2) (3) The following specifications apply for single supply with V+ = 5V, Maximum Gain (0 Attenuation), RL = 200Ω, VOUT = 4VPPD, fin = 200 MHz, High Power Mode, Boldface limits apply at temperature extremes. Symbol Parameter Min Conditions (4) Typ (5) Max (4) Units Dynamic Performance −3dB Bandwidth VOUT= 2 VPPD 1.
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LMH6522 www.ti.com SNOSB53D – JULY 2011 – REVISED MARCH 2013 5V Electrical Characteristics(1)(2)(3) (continued) The following specifications apply for single supply with V+ = 5V, Maximum Gain (0 Attenuation), RL = 200Ω, VOUT = 4VPPD, fin = 200 MHz, High Power Mode, Boldface limits apply at temperature extremes. Symbol Parameter Conditions Min (4) Typ (5) Max (4) Units mA Power Requirements ICC Supply Current 465 485 P Power 2.3 2.
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LMH6522 SNOSB53D – JULY 2011 – REVISED MARCH 2013 www.ti.
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LMH6522 www.ti.
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LMH6522 SNOSB53D – JULY 2011 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (TA = 25°C, V+ = 5V, RL = 200Ω, Maximum Gain, High Power, f= 200MHz; LMH6522 soldered onto LMH6522EVAL evaluation board, Unless Specified).
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LMH6522 www.ti.com SNOSB53D – JULY 2011 – REVISED MARCH 2013 Typical Performance Characteristics (continued) (TA = 25°C, V+ = 5V, RL = 200Ω, Maximum Gain, High Power, f= 200MHz; LMH6522 soldered onto LMH6522EVAL evaluation board, Unless Specified).
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LMH6522 SNOSB53D – JULY 2011 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) (TA = 25°C, V+ = 5V, RL = 200Ω, Maximum Gain, High Power, f= 200MHz; LMH6522 soldered onto LMH6522EVAL evaluation board, Unless Specified). HD2 vs Frequency, Low Power Mode -30 Ch A Ch B POUT= 10dBm Ch C -40 Ch D HD3 vs Frequency, Low Power Mode -20 -30 -60 -70 -50 -60 -80 -70 -90 -80 -100 -90 0 100 200 300 400 FREQUENCY (MHz) Figure 15. 500 0 100 200 300 400 FREQUENCY (MHz) Figure 16.
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LMH6522 www.ti.com SNOSB53D – JULY 2011 – REVISED MARCH 2013 Typical Performance Characteristics (continued) (TA = 25°C, V+ = 5V, RL = 200Ω, Maximum Gain, High Power, f= 200MHz; LMH6522 soldered onto LMH6522EVAL evaluation board, Unless Specified).
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LMH6522 SNOSB53D – JULY 2011 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) (TA = 25°C, V+ = 5V, RL = 200Ω, Maximum Gain, High Power, f= 200MHz; LMH6522 soldered onto LMH6522EVAL evaluation board, Unless Specified). Cumulative Amplitude Error 2.0 2 PHASE ERROR (Degrees) 1.5 AMPLITUDE ERROR (dB) Cumulative Phase Error 4 50 MHz 200 MHz 300 MHz 1.0 0.5 0.0 -0.5 0 -2 -4 50 MHz 200 MHz 300 MHz -6 -8 -10 -12 -14 -16 -1.0 6 11 16 21 ATTENUATION (dB) Figure 27.
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LMH6522 www.ti.com SNOSB53D – JULY 2011 – REVISED MARCH 2013 Typical Performance Characteristics (continued) (TA = 25°C, V+ = 5V, RL = 200Ω, Maximum Gain, High Power, f= 200MHz; LMH6522 soldered onto LMH6522EVAL evaluation board, Unless Specified). Gain Step Timing, 8dB Step 5 3 2 4 2 4 1 3 1 3 0 2 0 2 -1 1 -1 1 0 -2 10 20 30 40 50 60 TIME (ns) Figure 33. 70 VOUT(V) 80 0 0 10 Gain Step Timing, 4dB Step 30 40 50 60 TIME (ns) Figure 34.
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LMH6522 SNOSB53D – JULY 2011 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) (TA = 25°C, V+ = 5V, RL = 200Ω, Maximum Gain, High Power, f= 200MHz; LMH6522 soldered onto LMH6522EVAL evaluation board, Unless Specified). Input Impedance R jX |Z| INPUT IMPEDANCE ( ) 250 Output Impedance 150 Z = R + jX R jX |Z| 125 OUTPUT IMPEDANCE ( ) 300 200 150 100 50 0 -50 100 75 50 25 0 -25 -100 -50 0 100 200 300 400 FREQUENCY (MHz) Figure 39.
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LMH6522 www.ti.com SNOSB53D – JULY 2011 – REVISED MARCH 2013 APPLICATION INFORMATION 100: FILTER VCC 1 PH 0.01 PF RF 40.2: 100: 0.01 PF 100: FILTER ¼ LMH6522 ADC 40.2: 0.01 PF 0.01 PF 100: 1 PH LO 5 GAIN 0-4 ENABLE Figure 43. LMH6522 Typical Application INTRODUCTION The LMH6522 is a fully differential amplifier optimized for signal path applications up to 400 MHz. The LMH6522 has a 100Ω input and a low impedance output. The gain is digitally controlled over a 31 dB range from +26dB to −5dB.
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LMH6522 SNOSB53D – JULY 2011 – REVISED MARCH 2013 www.ti.com BASIC CONNECTIONS A voltage between 4.75 V and 5.25 V should be applied to the supply pin labeled +5V. Each supply pin should be decoupled with a low inductance, surface-mount ceramic capacitor of 0.01uF as close to the device as possible. Additional bypass capacitors of 0.1uF and 1nF are optional, but would provide bypassing over a wider frequency range.
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LMH6522 www.ti.com SNOSB53D – JULY 2011 – REVISED MARCH 2013 Excel can also be used for simple circuits; however, the “Analysis ToolPak” add-in must be installed to calculate complex numbers. http://www.circuitsage.com/matching/matcher2.html SOURCE IMPEDANCE = 100: f = 200 MHz ZAMP = (130 + j10): ZIN = (97.8-j1.5): 5V L1 LMH6522 ZAMP ZIN C1 L2 L1, L2 = 22 nH C1 = 4 pF 5 GAIN 0-4 Figure 46.
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LMH6522 SNOSB53D – JULY 2011 – REVISED MARCH 2013 www.ti.com The LMH6522 output pins require a DC path to ground. On the evaluation board, inductors are installed to provide proper output biasing. The bias current is approximately 36mA per output pin. The resistance of the output bias inductors will raise the output common mode slightly. An inductor with low resistance will keep the output bias voltage close to zero, so the DC resistance of the inductor chosen will be important.
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LMH6522 www.ti.com SNOSB53D – JULY 2011 – REVISED MARCH 2013 CASCADE OPERATION VCC VCC 1 PH 1 PH 0.01 PF 0.01 PF 100: VIN ¼ LMH6522 40.2: 100: 0.01 PF 0.01 PF ¼ LMH6522 VOUT 40.2: 0.01 PF 0.01 PF 1 PH 1 PH Figure 50. Schematic for Cascaded Amplifiers With four amplifiers in one package the LMH6522 is ideally configured for cascaded operation. By using two amplifiers in series additional gain range can be achieved.
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LMH6522 SNOSB53D – JULY 2011 – REVISED MARCH 2013 www.ti.com Table 1. Pins with Dual Functions (1) Pin MODE = 0 MODE = 1 45 A4 SDO* 46 A3 SDI 47 A2 CSb 48 A1 CLK (1) Pin 45 requires external bias. See Serial Mode Section for Details. PARALLEL INTERFACE Parallel mode offers the fastest gain update capability with the drawback of requiring the most board space dedicated to control lines. When designing a system that requires very fast gain changes parallel mode is the best selection.
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LMH6522 www.ti.com SNOSB53D – JULY 2011 – REVISED MARCH 2013 The CLK pin is the serial clock pin. It is used to register the input data that is presented on the SDI pin on the rising edge; and to source the output data on the SDO pin on the falling edge. User may disable clock and hold it in the low state, as long as the clock pulse-width minimum specification is not violated when the clock is enabled or disabled. The CSb pin is the chip select pin.
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LMH6522 SNOSB53D – JULY 2011 – REVISED MARCH 2013 www.ti.com Control Logic LMH6522 CLK CSb SDI Clock out Chip Select out Data Out Data In SDO R 20: V+ (Logic High) For SDO (MISO) pin only: 12 mA Max VOH = V+, VOL = (V+) - {0.012 * (R+20) + Vcesat} Vcesat ~= 0.2V Recommended: R = 300 Ohms to 2000 Ohms V+ (Logic) = 2.5V to 5V Figure 54. Internal Operation of the SDO pin R/Wb Read / Write bit. A value of 1 indicates a read operation, while a value of 0 indicates a write operation. Reserved Not used.
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LMH6522 www.ti.com SNOSB53D – JULY 2011 – REVISED MARCH 2013 tPL tPH 16th clock SCLK tSU SDI tH Valid Data Valid Data Figure 56. Write Timing Data Written to SDI Pin Table 3. Write Timing Data Input on SDI Pin Parameter Description tPL Minimum clock low time (clock duty dycle) tPH Minimum clock high time (clock duty cycle) tSU Input data setup time tH Input data hold time Table 4.
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LMH6522 SNOSB53D – JULY 2011 – REVISED MARCH 2013 www.ti.com THERMAL MANAGEMENT The LMH6522 is packaged in a thermally enhanced package. The exposed pad is connected to the GND pins. It is recommended, but not necessary, that the exposed pad be connected to the supply ground plane. In any case, the thermal dissipation of the device is largely dependent on the attachment of this pad to the system printed circuit board (PCB).
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LMH6522 www.ti.com SNOSB53D – JULY 2011 – REVISED MARCH 2013 Table 8. Filter Component Values (continued) R3, R4 100Ω 100Ω R1 100Ω C1 L1 AMP VOUT - 100Ω L5 C3 ADC ZIN R3 ADC VIN + R4 C2 L2 AMP VOUT + ADC VIN - R2 ADC VCM Figure 57. Sample Filter POWER SUPPLIES The LMH6522 was designed primarily to be operated on 5V power supplies. The voltage range for V+ is 4.75V to 5.25V. Power supply accuracy of 2.5% or better is advised.
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LMH6522 SNOSB53D – JULY 2011 – REVISED MARCH 2013 www.ti.
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LMH6522 www.ti.com SNOSB53D – JULY 2011 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision C (March 2013) to Revision D • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMH6522SQ/NOPB WQFN NJY 54 2000 330.0 16.4 5.8 10.3 1.0 12.0 16.0 Q1 LMH6522SQE/NOPB WQFN NJY 54 250 178.0 16.4 5.8 10.3 1.0 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH6522SQ/NOPB WQFN NJY 54 2000 367.0 367.0 38.0 LMH6522SQE/NOPB WQFN NJY 54 250 213.0 191.0 55.
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PACKAGE OUTLINE NJY0054A WQFN SCALE 2.000 WQFN 5.6 5.4 B A PIN 1 INDEX AREA 0.5 0.3 0.3 0.2 10.1 9.9 DETAIL OPTIONAL TERMINAL TYPICAL 0.8 MAX C SEATING PLANE 2X 4 SEE TERMINAL DETAIL 3.51±0.1 19 (0.1) 27 28 18 50X 0.5 7.5±0.1 2X 8.5 1 45 54 PIN 1 ID (OPTIONAL) 46 54X 54X 0.5 0.3 0.3 0.2 0.1 0.05 C A C B 4214993/A 07/2013 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2.
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EXAMPLE BOARD LAYOUT NJY0054A WQFN WQFN (3.51) SYMM 54X (0.6) 54 54X (0.25) SEE DETAILS 46 1 45 50X (0.5) (7.5) SYMM (9.8) (1.17) TYP 2X (1.16) 28 18 ( 0.2) TYP VIA 19 27 (1) TYP (5.3) LAND PATTERN EXAMPLE SCALE:8X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND METAL SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) METAL SOLDER MASK DEFINED SOLDER MASK DETAILS 4214993/A 07/2013 NOTES: (continued) 4.
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EXAMPLE STENCIL DESIGN NJY0054A WQFN WQFN SYMM METAL TYP (0.855) TYP 46 54 54X (0.6) 54X (0.25) 1 45 50X (0.5) (1.17) TYP SYMM (9.8) 12X (0.97) 18 28 19 27 12X (1.51) (5.3) SOLDERPASTE EXAMPLE BASED ON 0.125mm THICK STENCIL EXPOSED PAD 67% PRINTED SOLDER COVERAGE BY AREA SCALE:10X 4214993/A 07/2013 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.