Specifications

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SLWS142J − JANUARY 2003 − REVISED AUGUST 2007
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17.9 Programmable FIR, Gain, Transmit Input, and Receive Output Control Registers
The following tables detail the various control registers for a single PFIR filter. Note that the configuration software
calculates these registers. The PFIR has several sets of memories that are synchronized to read the data to be
filtered, and the coefficient memory. The Common Address Generator is used to read from the Forward and Reverse
Delay memory in each cell. This represents the data to be filtered. Different filtering modes, can have I or Q data at
different offset positions. The Coefficient Address generator is used to read the coefficient memory.
The Forward Read address and Forward Write address are used at the end of each computational cycle, to pass
the Forward Delay data between the FIR cells. The Forward Write strobe indicates the times within the PFIR
calculates that the data is written to the next cell.
The Backward Read address, Backward Write address, Backward End Cell Read address, Backward End Cell Write
address, and Backward End Cell Read Bypass are used to develop the address to pass the reverse delay line data
from the 16
th
FIR cell back towards the 1
st
FIR cell. The Backward Write strobe indicates the times within the PFIR
calculates that the data is written to the next cell.
Table 19. Coefficient Address Generator Page 0x12 Address 0x10
Rcv Tx FIELD BITS Dflt DESCRIPTION
E E coef_ofsc 3..0 FIR coefficient address offset
E E coef_modc 7..4 FIR coefficient modulo count
E E coef_repc 11..8 FIR coefficient repeat count
E E coef_sym 12 FIR hardware exploits symmetry (1) or not (0)
E E coef_zerofr 13 FIR zero forward read
Table 20. Common Address Generator Page 0x12 Address 0x11
Rcv Tx FIELD BITS Dflt DESCRIPTION
E E agen_recr 3..0 FIR recirculate count
E E agen_depd 7..4 FIR depth count
E E agen_modd 11..8 FIR modulo count
E E agen_togen 12 FIR toggle enable for back end read and write
Table 21. Forward Read Address Generator Page 0x12 Address 0x12
Rcv Tx FIELD BITS Dflt DESCRIPTION
E E fragen_soff 3..0 FIR forward read address generator offset
E E fragen_srecr 7..4 FIR forward read address generator recirculate count
E E fragen_sdepd 11..8 FIR forward read address generator depth count
E E fragen_stepn 15..12 FIR forward read address generator step
Table 22. Forward Write Address Generator Page 0x12 Address 0x13
Rcv Tx FIELD BITS Dflt DESCRIPTION
E E fwagen_soff 3..0 FIR forward write address generator offset
E E fwagen_srecr 7..4 FIR forward write address generator recirculate count
E E fwagen_sdepd 11..8 FIR forward write address generator depth count
E E fwagen_wrecrl 15..12 FIR forward write address generator step