Specifications

QSSC-S4R Technical Product Specification Hot Swap Backplane (HSBP)
75
AT24C64*
0xA0 VSC local bus Private SAS backplane FRU EEPROM
TPM75 0x90 VSC local bus Private SAS backplane temperature sensor
Table 23. Global I
2
C* bus Addresses (IPMB Bus)
Device Address Bus Description
VSC410* NA IPMB system interface VSC410* controller public IPMB bus
8.2.10 Resets
The principal reset for logic on the Hot-swap backplane is supplied by the PCI_RST_BP_N signal from the server
board via the HSBP 8-pin connector and two 20x2 FPFB connectors.
The PCA9554* device being used to control the fans, has an internal power-on reset that configures all its I/O pins as
inputs.
See the diagram below for reset flow.
Figure 26. Hot-swap Backplane Reset and Power Good Block Diagram
8.2.11 Clock Generation
The Hot-Swap Backplane requires one 4MHz crystal for the VSC410* controller.
8.2.12 Programmed Devices
There are two programmed devices on the Hot-swap backplane.
8.2.12.1 Flash Memory
The Flash memory device contains program code. The code is run by the VSC410* controller.
x Memory configuration: 64Mb SPI
8.2.12.2 Field Replaceable Unit (FRU)
The FRU is a serial EEPROM programmed at automated test equipment (ATE).
x Memory Configuration: 64Kb serial