Specifications

Memory Riser QSSC-S4R Technical Product Specification

4.2.2 DDR3 Functionality

Figure 15. DDR3 Interlace Block Diagram

DDR3 protocol and signaling, includes support for the following:

x Up to two RDIMMs per DDR3 bus

x Up to eight physical ranks per DDR3 bus (sixteen per Mill Brook)

x 800 MT/s or 1066 MT/s (both DDR3 buses must operate at the same frequency)

x Single Rank x4, Dual Rank x4, Single Rank x8, Dual Rank x8, Quad Rank x4, Quad Rank x8

x 1 GB, 2 GB, 4 GB, 8 GB, 16 GB DIMM

x DRAM device sizes: 1 GB, 2 GB

x Mixed DIMM types (no requirement that DIMMs must be the same type, except that all DIMMs attached to Mill

Brook must run with a common frequency and core timings). (Host lockstep requirements may impose additional

requirements on DIMMs on separate Intel

® SMI channels).

x DDR buses may contain different number of DIMMs, zero through two. (Host lockstep requirements may impose

additional requirements on DIMMs on separate Intel

® SMI channels).

x Cmd/Addr parity generation and error logging.

x No support for non-ECC DIMMs

x No support for DDR2 protocol and signaling

x Support for integrating RDIMM thermal sensor information into Intel

® SMI Status Frame.

Table 9. DPC Supported Configuration

CONFIG SLOT1 SLOT0

CONFIG-1 QR RDIMM QR RDIMM

CONFIG-2 DR RDIMM QR RDIMM

CONFIG-3 SR RDIMM QR RDIMM

CONFIG-5 DR RDIMM DR RDIMM

CONFIG-6 SR RDIMM DR RDIMM

CONFIG-8 DR RDIMM SR RDIMM

CONFIG-9 SR RDIMM SR RDIMM

CONFIG-10 Empty QR RDIMM

CONFIG-11 Empty DR RDIMM

CONFIG-12 Empty SR RDIMM