Specifications

QSSC-S4R Technical Product Specification Memory Riser
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Figure 14. QSSC-S4R Memory Riser Functional Block Diagram and DIMM Population Rules
4.2 Intel® 7500 Scalable Memory Buffer (Mill Brook) Functionality
4.2.1 Intel® Scalable Memory Interconnect Functionality
Intel® SMI protocol and signaling includes support for the following:
x 4.8 Gbs, 6.4 Gbs signaling forwarded clock fail-over NB and SB.
x 9 data lanes plus 1 CRC lane plus 1 spare lane SB.
x 12 data lanes plus 1 CRC lane plus 1 spare NB.
x Support for integrating RDIMM thermal sensor information into Intel
® SMI Status Frame.
x No support for daisy chaining (Mill Brook is the only Intel
® SMI device in the channel).
x No support for FB-DIMM1 protocol and signaling