Specifications

Main Board QSSC-S4R Technical Product Specification
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x After CPU and VTT VRs are enabled, as well as any memory riser presence signal asserted, a global VR enable is
asserted for memory risers, SAS Backpanel, and SAS Riser. An additional output for IO Riser power enable will be
asserted at the same time as the other adapters in the system.
x A signal internal to the PLD representing a system-wide powergood signal will be asserted once all FRU
powergood signals are asserted. This signal is inverted and used to enable clocks. The system powergood is
delayed 100ms before the PLD asserts an output for the SYS_PWRGD_PLD signal.
2.3.11.2 PCI Express Hot-plug
The main board PLD will implement delay functions for PCI Express hot plug functionality:
x 100ms timer delay for the 3.3V powergood signal from the Texas Instruments* TPS2363 going to each HP-enabled
PCI Express slot (1-2 and 6-7).
x Generate a 100ms delayed enable (based on slot’s 3.3V STBY rail) to the hot-plug isolation logic for slot SMB and
wake signals
2.3.12 Interrupt and Error Logic Block Diagram
Figure 6. Interrupt and Error Logic Block Diagram
2.3.13 Power Delivery Block Diagram
The main board takes in P12V (+12V) and P3V3_STBY (3.3V Standby) voltage rails from the system power distribution
board. These rails are used to generate the specialized power rails required by components on the main board and are
distributed through the main board to other boards in the board set. Figure 7. Mainboard Power Block Diagram shows
the power delivery flow used on the main board.