Specifications
iv
3.3.5 Chassis Intrusion .............................................................................................................................................................. 53
4. Memory Riser .......................................................................................................................... 54
4.1 System Memory Topology and Functional Diagram .............................................................................................. 54
4.2 Intel® 7500 Scalable Memory Buffer (Mill Brook) Functionality ............................................................................. 55
4.2.1 Intel® Scalable Memory Interconnect Functionality ......................................................................................................... 55
4.2.2 DDR3 Functionality .......................................................................................................................................................... 56
4.3 Functional Architecture ........................................................................................................................................... 57
4.3.1 Supported Memory Configurations ................................................................................................................................... 57
4.3.2 Temperature Sensors, FRU, and SPD ............................................................................................................................. 58
4.3.3 Memory Riser LEDs ......................................................................................................................................................... 58
4.3.4 Power Rails ...................................................................................................................................................................... 58
5. I/O Riser ................................................................................................................................... 59
5.1 I/O Riser Features .................................................................................................................................................. 59
5.2 Functional Architecture ........................................................................................................................................... 60
5.3 Video Subsystem .................................................................................................................................................... 60
5.3.1 Feature Overview ............................................................................................................................................................. 60
5.3.2 ServerEngines Pilot II IBMC Block Diagram ..................................................................................................................... 61
5.3.3 Video Disable Feature ...................................................................................................................................................... 61
5.3.4 Dual Video ........................................................................................................................................................................ 61
5.4 USB Subsystem ..................................................................................................................................................... 61
6. Intel® Remote Management Module 3 (RMM3) ...................................................................... 63
7. SAS Riser ................................................................................................................................ 65
7.1 Introduction ............................................................................................................................................................. 65
7.1.1 SAS Riser Features .......................................................................................................................................................... 65
7.2 Functional Architecture ........................................................................................................................................... 65
7.2.1 I²C Interface ..................................................................................................................................................................... 66
7.2.2 Host Interface ................................................................................................................................................................... 66
7.2.3 Internal SAS Interface ...................................................................................................................................................... 66
7.2.4 Memory Interface ............................................................................................................................................................. 67
7.2.5 Debug Jumpers ................................................................................................................................................................ 67
7.2.6 iBBU07 Remote Battery Backup for On-board Memory (optional) ................................................................................... 67
7.2.7 SAS Riser Power .............................................................................................................................................................. 67
8. Hot Swap Backplane (HSBP) .................................................................................................. 68
8.1 Introduction ............................................................................................................................................................. 68
8.1.1 Key Features .................................................................................................................................................................... 68
8.1.2 Placement View and LED Definition ................................................................................................................................. 69
8.1.3 Connector Signal Description and Pin-outs ...................................................................................................................... 70
8.2 Functional Architecture ........................................................................................................................................... 71
8.2.1 SAS Buses ....................................................................................................................................................................... 72
8.2.2 Hot-swap Backplane ........................................................................................................................................................ 72
8.2.3 Full-duplex Serial Mode Operation ................................................................................................................................... 72
8.2.4 SAS Controller.................................................................................................................................................................. 72
8.2.5 Vitesse* VSC410 Controller Functionality ........................................................................................................................ 73
8.2.6 SAS Drive Functionality .................................................................................................................................................... 73
8.2.7 Power Control Interlock .................................................................................................................................................... 73
8.2.8 SAS Enclosure Management ........................................................................................................................................... 74
8.2.9 Server Management Interface .......................................................................................................................................... 74
8.2.10 Resets ............................................................................................................................................................................ 75
8.2.11 Clock Generation ............................................................................................................................................................ 75
8.2.12 Programmed Devices ..................................................................................................................................................... 75
9. System Overview ..................................................................................................................... 76