Specifications

QSSC-S4R Technical Product Specification Main Board
37
The main board includes a 300 pin PCI Express super-slot custom connector to interface with the I/O riser card. To
communicate with the advanced firmware control (Intel
® Remote Management Module 3) the I/O riser connector will
have the following:
x Six SMbus
x Two USB buses connection to iBMC
x A video bus connection to front panel
x A LPC Bus
x Intel
® 82576-NS Gigabit Ethernet Controller (Kawela), PCI-E X1 to iBMC
Details on the I/O riser appear in “I/O Riser” on page 59.
2.3.5 SAS Sub-System Interface
The main board includes a 98 pin x8 pin PCI Express connector to interface with the x4PCIExpress* SAS Riser card.
This PCI Express slot is meant for the SAS Riser and is not to be used with any other type of PCI Express Standard
Adapter Card.
The SAS Riser hosts an LSI* SAS2108 (Liberator) ROC (RAID-On-a-Chip) Controller, at 800MHz. Details on the SAS
riser appear in SAS Riser chapter on page 65.
2.3.6 Clock Subsystem
The clock synthesizers and buffers covered in this section are used on Intel® Xeon® processor 7500 series-based
(Boxboro-EX) products. QSSC-S4R implements the CK410B+/DB1200/DB800/CKMNG combination. The selection of
components is specific to each product’s clocking and routing requirements.
2.3.6.1 High Speed Clocks and Differential Buffers:
x CK410B Clock generator/synthesizer
x DB1200 Host/CPU/IOH/MEM clock buffer
x DB1200/DB800 PCIe serial reference clock buffer
x CK MNG BMC+NIC clock buffer
The main board clock tree is generated from a single CK410B with spread spectrum capability. The CK410B generates
multiple copies of differential pair high-speed clocks (133MHz BCLK). The DB1200 (High BW / PLL mode) buffer
generates additional BCLK copies for the CPUs, XDP1, and IOH core.
The CK410B drives BCLKs to two DB1200 (High BW / PLL mode) for FBD clocking. Each FBD branch clock
input is fed by a DB1200 buffer. 16 DIMMs are driven by each buffer (8 on each of two risers). The CK410B also