Specifications

Main Board QSSC-S4R Technical Product Specification
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applications to run in independent partitions. A partition behaves like a virtual machine (VM) and provides isolation and
protection across partitions. Each partition is allocated its own subset of host physical memory.
2.3.1.16 System Management Bus (SMBus)
ICH10R contains an SMBus host interface that allows the processor to communicate with SMBus slaves. This interface
is compatible with most I
2
C devices. Special I
2
C commands are implemented.ICH10’s SMBus host controller provides
a mechanism for the processor to initiate communication with SMBus peripherals (slaves.) Also, ICH10R supports
slave functionality, including the Host Notify protocol. Hence, the host controller supports eight command protocols of
System Management Bus (SMBus) Specification, Version 2.0: Quick Command, Send Byte, Receive Byte, Write
Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify.ICH10R’s SMBus interface also
implements hardware-based Packet Error Checking for data robustness and Address Resolution Protocol (ARP) to
dynamically provide address to all SMBus devices.
2.3.1.17 General-Purpose I/O (GPIO)
Various GPIO’s are provided for custom system design. ICH10R contains up to 61 GPIO signals. Each GPIO can be
configured as an input or output signal. The number of I/O varies depending on the ICH10R configuration. Some
GPIO’s exist in the resume power plane. Care must be taken to make sure GPIO signals are not driven high into
power-down planes. Some ICH10R GPIO’s may be connected to pins on devices that exist in the core well. If these
GPIO’s are outputs, there is a danger that a loss of core power or a power button override event results in the ICH10R
driving a pin to a logic ‘1’ to another device that is powered down. The routing bits for GPIO[15:0] allow an input to the
routed to SMI# or SCI, or neither.
Note: a bit can be routed to either SMI# or SCI, but not both.
GPIO[15:1] have sticky bits on the input. As long as the signal goes active for at least two clock cycles, ICH10R keeps
the sticky status bit active. If the system is in S0 or S1 state, the inputs are sampled at 33MHz. In S3-S5 states, the
inputs are sampled at 32.768KHz. If the input signal is still active when the latch is cleared, it will again be set. Another
edge trigger is not required. This makes these signals level-triggered inputs.
2.3.2 PCI-Express Subsystem
PCIe I/O slots including the support circuits for:
x Four hot-swap PCIe Gen-2 x8 slots (Slot 1 - 2 & Slot 6 - 7)
x Three PCIe Gen-2 x4 slots (Slot 3 - 4 & 8)
x One PCIe Gen-2 x16 slot (Slot 5)
x Two PCIe Gen-1 x4 slots (Slot 9 - 10)
x One designated PCIe Gen-2 x8 slot for SAS riser board – in Enterprise SKU
All slots comply with PCI Express ™ Base Specification Rev 2.0. Refer to the PCI Express Specification Rev 2.0 for
further details.
2.3.3 Main Board Memory Riser Interface
The main board includes eight 230 pin connectors that interface with up to eight Memory Risers. Each of these
Memory Riser connectors are individually connected to two of the SMI channels. Serial Presence Detect (SPD) side-
band signals are also passed between the Memory Risers and the ICH.
The main board supports the following memory riser population configurations:
x Memory riser installed in one memory riser slot, with up to 8 DIMM slots populated.
x Memory risers installed in four of eight memory riser slots.
x Memory risers installed in all eight-riser slots.
x Other riser configurations are not supported because they will cause DIMM population violations and malfunctions
in memory riser DIMM fault LED operation.
2.3.4 Main Board I/O Riser Interface
The mainboard I/O riser connector supports one I/O Riser hosting the following:
x Optional Intel® RMM3 2/GCM3 advanced server management module
x Two Intel® 82576-NS PCIe based, dual-GbE LAN controllers (Kawela)