Specifications

Main Board QSSC-S4R Technical Product Specification
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2.3.1.1 Enterprise South Bridge Interface (ESI)
Enterprise South Bridge Interface (ESI) is the chip-to-chip connection between the IOH and ICH10. This high-speed
interface integrates advanced priority-based servicing allowing for concurrent traffic capabilities. Base functionality is
completely software transparent permitting current and legacy software to operate normally.
2.3.1.2 PCI Express
ICH10 provides up to six PCI Express Gen1 root ports. Each root port supports 2.5Gbit/s/lane/direction. PCI Express
root ports 1-4 can be statically configured as four x1 ports or ganged together to formonex4 port. Ports 5 and 6 can
only be used as two x1 ports.
The integrated gigabit Ethernet controller’s data lines for 1Gbit/s speed are multiplexed with PCI Express root port 6,
and therefore is unavailable if a gigabit Ethernet PHY is connected. The use of a 10/100Mbit/s PHY does not consume
PCI Express root port 6 and therefore the port is available to be utilized as a x1 port.
2.3.1.3 Serial ATA (SATA) Controller
ICH10 has two integrated SATA host controllers that support independent DMA operation on up to six ports, and
supports data transfer rates of up to 3.0Gb/s (300 MB/s.) The SATA controller supports two modes of operation -
legacy mode using I/O space and AHCI mode using memory space. Software that uses legacy mode will not have
AHCI capabilities. ICH10 supports Serial ATA Specification, Revision 1.0a. ICH10 also supports several optional
sections of Serial ATA II: Extensions to Serial ATA 1.0 Specification, Revision 1.0 (AHCI support is required for some
elements.)
2.3.1.4 Advanced Host Controller Interface (AHCI)
ICH10R provides hardware support for AHCI, a new programming interface for SATA host controllers. Platforms
supporting AHCI may take advantage of performance features such as no master/slave designation for SATA devices -
each device is treated as a master – and hardware-assisted native command queuing. AHCI also provides usability
enhancements such as hot-plug. AHCI requires appropriate software support (e.g., an AHCI driver) and for some
features, hardware support in the SATA devices or additional platform hardware.
2.3.1.5 Intel® Matrix Storage Technology
ICH10R provides support for Intel® Matrix Storage Technology, providing both AHCI and integrated RAID functionality.
The industry-leading RAID capability provides high-performance RAID 0, 1, 5, and 10 functionality on up to six SATA
ports. Matrix RAID support is provided to allow multiple RAID levels to be combined on a single set of hard drives, such
as RAID 0 and RAID 1 on two disks. Other RAID features include hot spare support, SMART alerting, and RAID 0
auto-replace.
2.3.1.6 PCI Interface
ICH10R’s PCI interface provides a 33MHz, Revision 2.3 implementation. ICH10R integrates a PCI arbiter that supports
up to four external PCI bus masters in addition to the internal ICH10R requests. This allows for combinations of up to
four PCI down devices and PCI slots.
2.3.1.7 Low Pin Count (LPC) Interface
ICH10R implements an LPC interface as described in LPC 1.1 Specification. The LPC bridge function of ICH10R
resides in PCI Device 31: Function 0. In addition to the LPC bridge interface function, D31:F0 contains other functional
units including DMA, interrupt controllers, timers, power management, system management, GPIO, and RTC.
2.3.1.8 Serial Peripheral Interface (SPI)
ICH10R implements an SPI interface as an alternative interface for the BIOS flash device. An SPI flash device can be
used as a replacement for the FWH, and is required to support gigabit Ethernet, Intel
® Active Management Technology
(AMT), and integrated Intel
® Quiet System Technology (QST.) ICH10R supports up to two SPI flash devices with speed
up to 33MHz utilizing two chip select pins.
2.3.1.9 Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)
ICH10R supports LPC DMA, which is similar to ISA DMA, through ICH10R’s DMA controller. LPC DMA is handled
through the use of LDRQ# lines from peripherals and special encoding on LAD[3:0] from the host. Single, Demand,
Verify, and Increment modes are supported on the LPC interface. Channels 0–3 are 8-bit channels. Channels 5–7 are
16-bit channels. Channel 4 is reserved as a generic bus master request.