Specifications

Main Board QSSC-S4R Technical Product Specification
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x8. If that attempt fails, an attempt is made at x4, then at x2 and finally at x1. Note that the x8, x4 and x2 link widths will
only use the LSB positions from lane 0, while a x1 link can be connect to any of the x positions (lane 0-3) providing a
higher tolerance to single point lane failures. When settling on a narrower width, the remaining links are unused. The
links will use the LSB wires of the physical layer to route the packets for the negotiated width.
2.2.2.4 Enterprise South Bridge Interface (ESI)
Enterprise South Bridge Interface (ESI) is the chip-to-chip connection between the IOH and ICH10. This high-speed
interface integrates advanced priority-based servicing allowing for concurrent traffic capabilities. Base functionality is
completely software transparent permitting current and legacy software to operate normally. The IOH ESI supports
features that are listed below in addition to the PCI Express specific messages:
y A chip-to-chip connection interface to ICH10
y 2GB/s point-to-point bandwidth (1GB/s each direction)
y 100MHz reference clock
y 62-bit downstream addressing.
y APIC and MSI interrupt messaging support. Will send Intel-defined “End of Interrupt” broadcast message
when initiated by the processor
y Message Signaled Interrupt (MSI) messages
y SMI, SCI, and SERR error indication
y Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port.
2.2.2.5 Controller Link (CL)
Controller Link is the private low pin count, low power communication interface between MEIOH and ME-ICH portions
of the ME (Management Engine) subsystem. This interface supports clocking at 33MHz with double data rate at
66MHz. The usage model for this interface requires lower power as it remains powered during even the lower power
states. Since PECI (Platform Environmental Control Interface) signals are routed through ICH10, these signals can
also be passed to ME-IOH over the CL interface. Firmware and data stored in the SPI flash memory connected to
ICH10 are also read over CL.
2.2.2.6 System Management Bus (SMBus)
The IOH includes an SMBus Specification, Revision 2.0 compliant slave port. This SMBus slave port provides server
management (SM) visibility into all configuration registers in the IOH. Like JTAG accesses, the IOH’s SMBus interface
is capable of both accessing the IOH registers and generating in-band downstream configuration cycles to other
components.
2.2.2.7 Reduced Media Independent Interface (RMII)
RMII is a standard, low pin count, low power interface. The IOH has a 10/100 MAC interface visible only to the
integrated Management Engine. The MAC interfaces provide an RMII interface to either an external PHY portion of
another MAC or a discrete PHY part. The interface utilizes a 50MHz clock that is typically sourced from the PHY to the
MAC. The clock may also be derived from an external source.
2.2.3 Intel® 7500 Scalable Memory Buffer
2.3 The Intel® 7500 Scalable Memory Buffer is discussed in detail in
“System Memory Topology and Functional Diagram
The following nomenclature is followed for DIMM population.
Figure XX