Specifications

QSSC-S4R Technical Product Specification Hot-Swap Controller (HSC) Architecture
313
30. Hot-Swap Controller (HSC) Architecture
The HSC uses a VSC410* SAF-TE enclosure processor (SEP). This microcontroller employs a v3000 RISC CPU, 8 KB
of internal SRAM, GPIO, SGPIO, two general purpose UARTs, one SPI, and four I
2
C compatible interfaces.
Figure 111. HSC Interface Routing
* If present, SGPIO is disconnected.
** If present, I
2
C3 is disconnected.
30.1.1 I2C Interfaces
The VSC410 supports four I
2
C compatible serial interfaces. These multi-master interfaces are configured in firmware to
operate at 100 KHz. Optional support functions, such as I
2
C bus cleanups, can be configured in firmware.
Table 203. I
2
C Bus Assignments
I
2
C Bus Number Connection Protocol Connected Device(s)
I
2
C0 Reserved None
I
2
C1 Master / slave I
2
C (private bus)
Temperature sensor, NV/FRU
EEPROM
I
2
C2 IPMB Baseboard management controller
I
2
C3 SES2-over-I
2
C, SAFTE Host bus adapter
30.1.2 Serial Peripheral Interface (SPI)
The VSC410 SPI accesses operational code in a separate SPI-compatible EEPROM device. This interface is private
and can only be accessed by the HSC to retrieve or update firmware.
30.1.3 GPIO Pins
Twenty GPIO pins are on the VSC410:
x Eight for drive presence detection
x Eight are for LED control
x One for write protection control for both the SPI and I
2
C EEPROM devices
x Two for SFF-8087 cable detection via side-band ground pins
x Serial General-purpose Input / Output (SGPIO)
The VSC410 supports serial GPIO (SGPIO). This four-wire bus provides the status for up to 32 disks via a series of
fault / locate / active bits. The hot-swap controller supports two SGPIO interfaces (SGPIO0 and SGPIO1), according to
the SFF-8485 specification. Each SGPIO interface provides disks status for four disks. This implementation supports
only SGPIO communication from the host bus adapter (HBA) to the HSC (simplex).