Specifications

QSSC-S4R Technical Product Specification Main Board
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Figure 3 Intel® 7500 Chipset High-Level Block Diagram
2.2.2.2 Intel® QPI Features
Two full-width Intel® QPI link interfaces:
x Packetized protocol with 18 data/protocol bits and 2 CRC bits per link per direction
x 4.8 GT/s, 5.86 GT/s and 6.4 GT/s supporting different routing lengths.
x Fully-coherent write cache with inbound write combining
x Read Current command support
x Support for 64-byte cache-line size
2.2.2.3 Integrated Manageability Engine (ME) PCI Express
Two x16 PCI Express Gen2 ports each supporting up to 8 GB/s/direction peak bandwidth All ports are configurable as
two independent x8 or four independent x4 interfaces An additional x4 PCI Express Gen2 port configurable to 2 x2
interfaces. An additional x4 PCI Express Gen1 port on non-legacy IOHs. This port is the ESI port on legacy IOHs Dual
unidirectional links Supports PCI Express Gen1 and Gen2 transfer rates full peer-to-peer support between PCI Express
interfaces. Support for multiple unordered inbound traffic streams. Support for Relaxed Ordering attribute. Full support
for software-initiated PCI Express power management x8 Server I/O Module (SIOM) support.
Table 4. Boxboro-EX PCI Express Port Configuration
PCI
EXPRESS
PORTS
CLOCKING
SOURCE
PORT CONFIGURATION
PE0/DMI EDI CLK NOT COMBINABLE
PE1
PECLK0
X2
X4
PE2 X2
PE3 X4
X8
X16
PE4 X4
PE5 X4
X8
PE6 X4
PE7
PECLK1
X4
X8
X16
PE8 X4
PE9 X4 X8
PE10 X4
The PCI Express Base Specification, Revision 2.0a requires that a port be capable of negotiating and operating at the
native width and x1. The IOH supports x16, x8, x4, x2 and x1 link widths for its PCI Express ports. During link training,
the IOH will attempt link negotiation starting from its native link width from the highest width and ramp down to the
nearest supported link width that passes negotiation. For example, a port strapped at x8 will first attempt negotiation at