Specifications
QSSC-S4R Technical Product Specification Contents
iii
Contents
1. Introduction .............................................................................................................................. 21
1.1 Document Organization .......................................................................................................................................... 21
1.2 System Overview .................................................................................................................................................... 21
1.3 System Features .................................................................................................................................................... 21
2. Main Board .............................................................................................................................. 23
2.1 Introduction ............................................................................................................................................................. 23
2.1.1 Main Board Block Diagram ............................................................................................................................................... 23
2.1.2 Main Board Major Component Placement ........................................................................................................................ 25
2.2 Functional Architecture ........................................................................................................................................... 27
2.2.1 Intel® Xeon® 7500 Processors ........................................................................................................................................ 27
2.2.2 Intel® 7500 Chipset .......................................................................................................................................................... 30
2.2.3 Intel® 7500 Scalable Memory Buffer ................................................................................................................................ 32
2.2.4 ICH10R Southbridge ........................................................................................................................................................ 33
2.2.5 PCI-Express Subsystem .................................................................................................................................................. 36
2.2.6 Main Board Memory Riser Interface ................................................................................................................................. 36
2.2.7 Main Board I/O Riser Interface ......................................................................................................................................... 36
2.2.8 SAS Sub-System Interface ............................................................................................................................................... 37
2.2.9 Clock Subsystem .............................................................................................................................................................. 37
2.2.10 Serial-ATA (SATA) Sub-system ..................................................................................................................................... 40
2.2.11 BIOS Flash Devices ....................................................................................................................................................... 40
2.2.12 USB 2.0 Subsystem ....................................................................................................................................................... 40
2.2.13 Post Code LEDs ............................................................................................................................................................. 41
2.2.14 Programmable Logic Devices (PLDs) ............................................................................................................................ 41
2.2.15 Interrupt and Error Logic Block Diagram ........................................................................................................................ 42
2.2.16 Power Delivery Block Diagram ....................................................................................................................................... 42
2.2.17 Reset and Powergood Diagram ..................................................................................................................................... 44
2.2.18 Power Sequencing/Timing Diagrams ............................................................................................................................. 45
2.2.19 Thermal Specifications ................................................................................................................................................... 45
3. Main Board Server Management ............................................................................................. 47
3.1 Introduction ............................................................................................................................................................. 47
3.1.1 IPMI 2.0 Features ............................................................................................................................................................. 47
3.1.2 Non IPMI Features ........................................................................................................................................................... 48
3.2 Functional Architecture ........................................................................................................................................... 49
3.2.1 Server Management Block Diagram ................................................................................................................................. 49
3.2.2 SMBus Block Diagram ..................................................................................................................................................... 50
3.2.3 Hardware Monitoring Block Diagram ................................................................................................................................ 51
3.2.4 Sensor Data Record SDR (SDR) Repository ................................................................................................................... 51
3.2.5 Field Replaceable Unit (FRU) Inventory Devices ............................................................................................................. 51
3.2.6 System Event Log (SEL) .................................................................................................................................................. 52
3.2.7 Real-Time Clock (RTC) Access........................................................................................................................................ 52
3.3 Supported Features ................................................................................................................................................ 52
3.3.1 Fan Speed Control ........................................................................................................................................................... 52
3.3.2 PECI ................................................................................................................................................................................. 52
3.3.3 CPU Throttling .................................................................................................................................................................. 52
3.3.4 Memory Throttling ............................................................................................................................................................ 53