Specifications

QSSC-S4R Technical Product Specification BMC Messaging Interfaces
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25.6.2 Receive Message Queue
The receive message queue is only accessible via t he SMS in t er f ace since t ha t in t er f ace is t he BMC’s hos t / sys t em
in t er f ace . The queue is t wo en t ries in size . Per- channel queue slo t s are no t provided .
25.6.3 SMS / SMM Status Register
Bi t s in t he s t a t us regis t er provide in t er f ace and pro t ocol s t a t e in f orma t ion . As an ex t ension t o t he I PM I 2 . 0 KCS
in t er f ace de f ini t ion , t he OEM1 and OEM2 bi t s in t he SMS and SMM in t er f aces have been de f ined t o provide BMC
s t a t us in f orma t ion . Table 196. SMS / SMM Status Register Bits s ummarizes t he f unc t ions o f t he s t a t us regis t er bi t s .
Read / wri t e is f rom t he perspec t ive o f t he hos t in t er f ace . All s t a t us regis t er bi t s are read-only t o t he hos t.
Table 196. SMS / SMM Status Register Bits
Bit Name Description
7 S1 Bits 7 and 6 indicate the current state of this KCS interface. The host
software examines these bits to verify that they are in sync with the
BMC. For more information on these bits, refer to the Intelligent
Platform Management Interface Specification Second
Generation v2.0.
6 S0
5 BMC State
1 (OEM2)
These bits provide a status indication of BMC health:
00b – BMC ready
01b – BMC hardware error (i.e., BMC memory test error)
10b – BMC firmware checksum error
11b – BMC is not ready
4 BMC State
0 (OEM1)
3 C/D# Bit 3 specifies whether the last write was to the command register or
the Data_In register (1=command, 0=data). It is set by hardware to
indicate whether last write from the host was to command or Data_In
register.
2 SMS_ATN
/
SMM_AT
N
When the status register is used for an SMS interface, the SMS_ATN
bit indicates that the BMC has a message for the SMS.
When the status register is used for an SMM interface, the
SMM_ATN bit indicates that the BMC has a message for the SMI
handler.
Set this bit to 1 when the BMC has a message for the SMS / SMI
handler. See Sub-sections 25.6.3 and 25.6.4 for more details on
these flag bits.
1 IBF Input buffer is full. Set this bit to 1 when either the associated
command or Data_In Register has been written by system-side
software. Cleared to 0 by the BMC reading the data register.
0 OBF Output buffer is full. Set this bit to 1 when the associated Data_Out
register is written by the BMC. Cleared to 0 by the host reading the
data register.
No t e : When t he BMC is rese t f rom ei t her a power-on or a hard rese t, t he pro t ocol s t a t e bi t s (S0 , S1) are ini t ialized t o
11b–Error S t a t e and t he BMC s t a t e bi t s (BMC S t a t e 0 / 1) are ini t ialized t o 00b – BMC Ready . This allows hos t
so ft ware t o de t ec t t ha t t he BMC has been rese t and t ha t t he BMC has t ermina t ed any in-process messages .
The BMC s t a t e bi t s are se t t o 11b – BMC no t ready i f t he BMC is busy ; such as during SEL or SDR erasure or while
t he I ni t ializa t ion Agen t is running .
25.6.4 Server Management Software (SMS) Interface
The SMS in t er f ace is t he BMC hos t in t er f ace . The BMC implemen t s t he SMS KCS in t er f ace as described in t he
I n t elligen t Pla tf orm Managemen t I n t er f ace Speci f ica t ion Second Genera t ion v2 . 0 . The BMC implemen t s t he op t ional
Ge t S t a t us / Abor t t ransac t ion on t his in t er f ace . Only logical uni t number (LUN) 0 is suppor t ed on t his in t er f ace .
Wi t h t he Se t BMC Global Enables command , t he BMC can genera t e an in t errup t reques t ing a tt en t ion when se tt ing
t he SMS_ATN bi t in t he s t a t us regis t er .
The SMS_ATN bi t t ha t is se t indica t es one or more o f t he f ollowing :
x
There is a t leas t one message in t he BMC receive message queue