Specifications

QSSC-S4R Technical Product Specification Processor Presence and Population Check
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All processors in a system have their CATERR pins tied together. The pin is used as a communication path to signal a
catastrophic system event to all CPUs. The BMC has direct access to this aggregate CATERR signal. The BMC only
monitors for the “CATERR held low” condition. A pulsed low condition is ignored by the BMC.
If a CATERR-low condition is detected, the BMC logs an error message to the SEL against the CATERR sensor. The
BMC logs a SEL entry, and resets the system. Because the CATERR signals are tied together, the BMC is unable to
determine which processor caused the CATERR event.
The sensor is rearmed on power-on (AC or DC power on transitions). It is not rearmed on system resets to avoid
multiple SEL events that could occur due to a potential reset loop if the CATERR keeps recurring, which would be the
case if the CATERR was due to an MSID mismatch condition.
24.35 CMOS Battery Monitoring
The BMC monitors the voltage level from the CMOS battery; which provides battery backup to the chipset RTC. This is
monitored as an auto-rearm threshold sensor. See the “BB VBat” sensor in Table 202. IBMC Core Sensors.