Specifications
QSSC-S4R Technical Product Specification Processor Presence and Population Check
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In order for the BMC to handle these values in its fan speed control algorithms, any Tcontrol SDRs referencing these
sensors must have the signed sensor flag bit set. The clamp temperature in the SDR is interpreted as a two’s-
complement signed integer.
24.15 IOH thermal Margin Sensor
QSSC-S4R platform supports two IOH, and each IOH supports on-die thermal sensor. The IPMI sensor reading is the
negative of the corresponding IOH thermal sensor.
24.16 Memory Buffer Thermal Margin Sensor
QSSC-S4R supports maximum eight memory risers. Each memory riser has two memory buffer devices. Among
others capabilities, this component provides an on-die thermal sensor.
SDRs for these aggregate sensors should be set to “sensor scanning disabled” state and that enabling/disabling of the
sensors occurs by the BMC FW when BIOS updates DIMM map using “Set Fan Control Configuration” command.
During POST, BIOS must send memory buffers population along with DIMM population to BMC using “Set Fan Control
Configuration” OEM command, this is even applied during memory hot plug and online/offline memory operation. BMC
will enable the corresponding aggregate memory buffer temperature sensor if and only if at least one of the associated
memory buffer devices is present.
BMC will monitor the temperature sensors for memory buffers devices regardless of the presence of any associated
DIMMs.
The BMC aggregates the calculated thermal margins for the memory buffers devices in a similar fashion as is done for
the DIMM thermal margins, with one aggregate IPMI sensor each for memory risers 1&2, 3&4, 5&6,and 7&8. The most
positive margin of a group of Mill Brook components is taken as the dominant margin. This value then becomes the
value of the associated memory buffer aggregate thermal margin sensor. This sensor is implemented as auto rearm.
24.17 Add In Card Thermal Margin Sensor
The BMC implements one IPMI thermal sensor for add-in card zone-1. BMC calculates add in card thermal margin
sensor from 3 physical discrete sensors (2 on the baseboard and 1 on the IO Riser card). This IPMI sensor value is
calculated according to the following equation:
Sensor value = T2 – T1 + Tio
T2 and T1 are discrete LM75 sensors located in add-in card zone-2 and zone-1 respectively. Tio is the discrete sensor
located on IO riser board.
The IPMI sensor is implemented as an auto-rearm threshold sensor.
24.18 Power Throttle Sensor
The BMC supports a PLD Power Throttle sensor which is used to log a SEL event when memory controller and/or the
CPUs are throttled encountering an over power drawn condition for the given power supply configuration and
capabilities. When power supply utilization is more than 80% of throttling limits, PDB FW will notify the PLD
immediately and PLD FW will decide the system need throttle memory controller and/or the CPUs or not. Moreover the
throttling limits are established by the PDB controller based on the number of PSU installed and not based on the
FRUSDR setup of the power supply configuration.
The power supply redundancy configuration in FRUSDR setup only influenced the SEL and the system status LED.
System will throttle Memory controller when:
x All 4x power supplies are not installed in the system OR multiple power supplies failed even though all 4x power
supplies are installed (Don’t assert this signal with three or more functional power supplies)
AND
x Memory VR current trip point (default setting: 90% of supported TDP current) is triggered.
AND
x System power utilization is high and exceeds a pre-set limit of 80%
System will throttle CPU when ·
x All 4x power supplies are not installed in the system OR multiple power supplies failed even though all 4x power
supplies are installed (Don’t assert this signal with three or more functional power supplies)