Specifications

Processor Presence and Population Check QSSC-S4R Technical Product Specification
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Upon BMC initialization, the processor presence offset is initialized to the deasserted state. The BMC then checks to
see if the processor is present, setting the offset accordingly. This state is updated at each DC power-on and at system
resets. If a processor is removed while the system has AC power, and the system is then powered-on (DC-on), the
appropriate deassertion event will be logged (if enabled). The net effect is that there should be one event logged for
processor presence at BMC initialization for each installed processor, assuming the SDR is configured to generate the
event. No additional events for processor presence are expected unless the sensor is manually re-armed using an
IPMI command.
24.11.1.2 Thermtrip Monitoring
When a thermtrip occurs it is detected by the IOH and the system hardware will attempt to power-down the system.
The BMC latches the thermtrip signal to retain a history for each processor. This history tracks whether the processor
has had a thermtrip since the last processor sensor re-arm or retest. If the BMC detects that a thermtrip occurred, then
it sets the thermtrip offset for the applicable processor status sensor.
Thermtrip signal latching is not persistent across AC or DC cycles.
24.11.2 Processor VRD Over-Temperature Sensor
This sensor monitors a digital signal that indicates whether a processor VRD is running over-temperature.
24.11.3 Digital Thermal Sensor
The processor supports a digital thermal sensor that provides a relative temperature reading that is defined as the
number of degrees below the processor’s thermal throttling trip point, also called the PROCHOT threshold. When a
processor reaches this temperature, the processor’s PROCHOT signal asserts, indicating that one or more of the
processor’s built-in Thermal Control Circuits (TCC) has been activated to limit further increases in temperature by
throttling the processor.
The digital thermal sensor reading value is always less than or equal to zero. A reading of zero indicates that the
PROCHOT threshold has been reached. The reading remains at zero until the temperature goes back below the
PROCHOT threshold.
The digital thermal sensors are located on the processor Platform Environment Control Interface (PECI) bus.
The readings are capped at the core’s thermal throttling trip point (reading = 0), so thresholds are not set and alert
generation is not enabled for these sensors.
24.11.3.1 PECI Interface
The platform environment control interface (PECI) is a one-wire, self-clocked bus interface that provides a
communication channel between Intel® Architecture Processors and chipset components to the BMC’s integrated
PECI subsystem. The PECI bus communicates environmental information, such as temperature data, between the
managed components, referred to as the PECI client devices, and the management controller, referred to as the PECI
system host. The PECI standard supersedes older methods, such as the thermal diode, for gathering thermal data.
See the Platform Environment Control Interface (PECI) Reference Firmware External Architecture Specification for
more information about this interface standard.
24.11.4 Processor Thermal Control Monitoring (Prochot)
The BMC monitors the processor’s internal thermal controls. The BMC provides this functionality by reading the
percentage of time that the processor ProcHot signal is asserted over a given measurement window (set to 5.8
seconds). This provides a value greater than or equal to zero.
The BMC implements this as a threshold sensor (IPMI sensor type = processor, sensor name = Therm Margin) on a
per-processor basis. This sensor supports one threshold, the upper-critical, and it is set for 50% by default in the
SDRs.
On QSSC-S4R there is hardware logic that detects when any one CPU is generating a PROC HOT signal which will
then force all four processors into throttling via a common FORCE_PR signal assertion.
24.12 Voltage Monitoring
The BMC provides voltage monitoring capability for voltage sources on the main board and processors such that all
major areas of the system are covered. This monitoring capability is instantiated in the form of IPMI analog/threshold
sensors.