Specifications

QSSC-S4R Technical Product Specification Processor Presence and Population Check
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24.5 BMC Internal Timestamp Clock
The BMC maintains a four-byte internal timestamp clock. The timestamp value is derived from an RTC element that is
internal to the BMC.
This internal timestamp clock is read and set using the Get SEL Time and Set SEL Time commands, respectively. The
Get SDR Time command can also be used to read the timestamp clock. These commands and the IPMI time format
are specified in the Intelligent Platform Management Interface Specification Second Generation v2.0.
24.5.1 BMC Clock Initialization
During system initialization the BMC cannot guarantee the validity of its internal timestamp, so it resets its clock
counter to zero. The BMC attempts to retrieve the current time from an internal battery-backed RTC element. If the
RTC time is in the pre-init range of 0 to 0x20000000, then the BMC ignores it and continues counting from zero, and
any SEL events have pre-init timestamps relative to the approximate time of the BMC initialization.
Whenever the BMC receives the Set SEL Time command, it updates the integrated RTC value. This helps ensure that
the BMC internal clock maintains synchronization with the system clock across BMC initializations. Using the Set SEL
Time command to force the BMC to a pre-init timestamp causes the RTC to be updated with the same value. Unless
the Set SEL Time command is sent with a valid time before the next BMC initialization, the BMC ignores the pre-init
time stored in the RTC.
24.5.2 System Clock Synchronization
The BMC does not have direct access to the system clock used by BIOS and the operating system. The BIOS must
send the Set SEL Time command with the current system time to the BMC during system Power-on Self Test (POST).
Synchronization during very early POST is preferred, so any SEL entries recorded during system boot can be
accurately time stamped.
If the time is modified through an OS interface, then the BMC’s time is not synchronized until the next system reboot.
24.6 System Event Log (SEL)
The BMC implements the system event log as specified in the Intelligent Platform Management Interface Specification,
Version 2.0. The SEL is accessible regardless of the system power state via the BMC's in-band and out-of-band
interfaces.
The BMC allocates 65,502 bytes (approx 64 KB) of non-volatile storage space to store system events. Each record is
padded with a four-byte timestamp that indicates when the record was created. The SEL timestamps might not be in
order. Up to 3,639 SEL records can be stored at a time. Any command that would result in an overflow of the SEL
beyond the allocated space will be rejected with an “Out of Space” IPMI completion code (C4h).
24.6.1 Servicing Events
Events can be received while the SEL is being cleared. The BMC implements an event message queue to avoid the
loss of messages. Up to three messages can be queued before messages are overwritten. The BMC recognizes
duplicate event messages by comparing sequence numbers and the message source. See the Intelligent Platform
Management Interface Specification Second Generation v2.0. Duplicate event messages are discarded (filtered) by the
BMC after they are read from the event message queue. The queue can contain duplicate messages.
24.6.2 SEL Entry Deletion
The BMC does not support individual SEL entry deletion. The SEL may only be cleared as a whole.
24.6.3 SEL Erasure
SEL erasure is a background process. After initiating erasure with the Clear SEL command, additional Clear SEL
commands must be executed to get the erasure status and determine when the SEL erasure is completed. This may
take several seconds. SEL events that arrive during the erasure process are queued until the erasure is complete and
then committed to the SEL. SEL erasure generates an Event Logging Disabled (Log Area Reset / Cleared offset)
sensor event.
24.7 Sensor Data Record (SDR) Repository
The BMC implements the sensor data record (SDR) repository as specified in the Intelligent Platform Management
Interface Specification, Version 2.0. The SDR is accessible through the BMC’s in-band and out-of-band interfaces