Specifications

BMC Functional Specifications QSSC-S4R Technical Product Specification
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After the BIOS has identified and saved the BSP information, it sets the FRB2 timer use bit and loads the watchdog
timer with the new timeout interval.
If the watchdog timer expires while the watchdog use bit is set to FRB2, the BMC (if so configured) logs a watchdog
expiration event showing the FRB2 timeout in the event data bytes. The BMC then hard resets the system, assuming
the BIOS selected reset as the watchdog timeout action.
The BIOS is responsible for disabling the FRB2 timeout before initiating the option ROM scan and before displaying a
request for a boot password. If the processor fails and causes an FRB2 time-out, the BMC resets the system.
The BIOS gets the watchdog expiration status from the BMC. If the status shows an expired FRB2 timer, the BIOS
enters the failure in the system event log (SEL). In the OEM bytes entry in the SEL, the last POST code generated
during the previous boot attempt is written. FRB2 failure is not reflected in the processor status sensor value.
The FRB2 failure does not affect the front panel LEDs.
23.5.2.1 Watchdog Timer Timeout Reason Bits
To implement FRB2, during POST the BIOS determines if a BMC watchdog timer timeout occurred on the previous
boot attempt. If it finds a watchdog timeout did occur, it determines whether that timeout was an FRB2 timeout, a
system management software (SMS) timeout, or an intentional, timed hard reset. The BMC provides the IPMI Get
Watchdog Timer command to facilitate determining the cause of the watchdog time out.
The BMC maintains the timeout-reason bits across system resets and DC power cycles, but not across AC power
cycles.