Specifications

QSSC-S4R Technical Product Specification BMC Functional Specifications
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BMC reset IPMI command No Yes
23.3.3 Front Panel System Reset
The reset button is a momentary contact button on the front panel. Its signal is routed through the front panel connector
to the BMC, which monitors and de-bounces it. The signal must be stable for at least 16 ms before a state change is
recognized.
If the reset button is locked by the BMC, then the button will not reset the system.
23.3.4 Soft Reset and Hard Reset
The BMC monitors a BIOS signal called BIOS_POST_CMPLT_N, which deasserts at the beginning of POST and
asserts at the end of POST. The signal deassertion indicates that a system reset has occurred. The BMC monitors this
signal to detect hard resets.
Soft resets, caused by assertion of the processor INIT pin, or keyboard <CTRL> + <ALT> + <DEL>, are converted by
BIOS into CF9 resets. The BMC records these reset types as “OEM” type resets, as defined in the Intelligent Platform
Management Interface Specification Second Generation v2.0, Tables 28-11.
The BMC detects these resets but does not participate in the reset mechanism.
23.3.5 BMC Command to Cause System Reset
Chassis Control is the primary command used to reset the system.
23.3.6 Watchdog Timer Expiration
The watchdog timer can be configured to cause a system reset when the timer expires. See the Intelligent Platform
Management Interface Specification, Version 2.0.
23.4 BMC Reset Control
23.4.1 BMC Exits Firmware Update Mode
The BMC firmware can be updated using firmware transfer commands through the LPC interface. The BMC enters
firmware transfer mode if it detects that the Force Update signal is asserted during initialization or if the operation code
checksum validation fails. When exiting firmware transfer mode, the BMC resets. The BMC re-synchronizes to the
state of the processor and power control signals it finds when it initializes.
23.4.2 Standby Power Comes Up
The system has AC power applied, but the system is not up. The BMC resets the system when DC power output from
the power supplies is available. The BMC re-synchronizes to the state of the processor and power control signals it
finds when it initializes.
23.5 System Initialization
The following items are initialized by both the BIOS and the BMC during system initialization.
23.5.1 Processor TControl Setting
Processors used with this chipset implement a feature called Tcontrol, which provides a processor-specific value that
can be used to adjust the fan control behavior to achieve optimum cooling and acoustics. The BMC reads these values
directly from the CPU via PECI. The BMC uses these values as part of the fan speed control algorithm. See Section
24.13.4.2.
23.5.2 Fault Resilient Booting (FRB)
Fault resilient booting (FRB) is a set of BIOS and BMC algorithms and hardware support that allow a multiprocessor
system to boot even if the bootstrap processor (BSP) fails. Only FRB2 is supported, using watchdog timer commands.
FRB2 refers to the FRB algorithm that detects system failures during the POST. The BIOS uses the BMC watchdog
timer to back up its operation during POST. The BIOS configures the watchdog timer to indicate that the BIOS is using
the timer for the FRB2 phase of the boot operation.