Specifications

BMC Functional Specifications QSSC-S4R Technical Product Specification
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must also coincide with the assertion of the “CPU Power Failure Status” bit in the chipset. Note that BIOS must de-
assert the “CPU Power Failure Status” bit on a normal power-on.
If the BMC detects a power-good dropout, the following occurs:
1. Hardware powers down the system.
2. The BMC asserts the Power Unit Failure offset of the Power Unit sensor and logs a SEL event. See Section
24.25.1.4.
3. The BMC generates a beep code for a Power Fault. See Table 179.
The BMC waits 10 seconds. If the power state retention feature is configured to power on the server after an AC
loss, it attempts to power up the server.
The BMC responds to the power loss interrupt within 1-2 ms if it is in operational mode.
23.1.3 Power up Sequence
To power up the system, the BMC simulates the front panel power button press by disabling the power button
passthrough mode temporary, generating a 200 ms pulse of the power button signal (Pilot II internally triggers a 100
ms pulse on each valid wakeup event; we double the length for the button press signals), and checking the
PS_PWRGD assertion. If the PS_PWRGD is not asserted, it waits for a second before retrying the power-up sequence
again for a maximum of eight retries, with a total duration of approximately 9.6 seconds. If the PS_PWRGD is still not
asserted at the end of the eight retries, a fault is generated.
After simulating the front panel power button press, the BMC initializes all sensors to their power-on initialization state.
The initialization agent is run. The firmware handles this sequence.
23.1.4 Power Down Sequence
To power down the system, the BMC simulates the front panel power button press by disabling the power button pass-
through mode, generating a 200 ms pulse of the power button signal, and checking the PS_PWRGD drop. If the
PS_PWRGD does not drop as expected, it waits for a second before sending another 200 ms pulse of the power
button signal for a maximum of eight retries. After the eight retires, if the PS_PWRGD is still asserted, the BMC will
force the simulation of the power button 4-second override mode. This guarantees that the system will be powered off
after the failure of eight power-down retries. A fault is not generated.
Before initiating the system power down, the BMC stops scanning any sensors that should not be scanned in the
powered-down state.
To power cycle the system via the IPMI command, the BMC simulates the front panel power button to (1) power down
the system, (2) wait for a second, and then (3) power up the system. Similar to the power-up sequence, if the BMC
failed to power down the system, it takes control by changing the ONCTLn signal. After a 5-second wait, the BMC
gives control back to the external APCI logic. The system will be powered up by the SLPS3n/SLPS5n signals. The
firmware handles this sequence.
23.1.5 Power Control Sources
The following sources can initiate power-up and / or power-down activity.
Table 172. Power Control Sources
Source External Signal Name or Internal
Sub Sub-system
Capabilities
Power button Front panel power button Turns power on or off
BMC watchdog timer Internal BMC timer Turns power off, or power cycle
Command Routed through command
processor
Turns power on or off, or power
cycle
Power state retention Implemented via BMC internal logic Turns power on when AC power
returns
Chipset Sleep S4 / S5 signal (same as
POWER_ON)
Turns power on or off
CPU Thermal CPU Thermtrip Turns power off