Specifications

QSSC-S4R Technical Product Specification BMC Functional Specifications
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23. BMC Functional Specifications
23.1 Power System
The BMC is in-line with the system power control path. This is implemented by an integrated hardware signal pass-
through. The pass-through allows the BMC to directly block power-on if necessary. If the BMC firmware is non-
functional, the default state of the pass-through hardware is to allow full system control. This is to provide a means of
power control in case a BMC firmware recovery is necessary.
The following block diagram shows the power and reset signal interconnections to the BMC. The signals names and
interconnections may not match the names in schematics. These are chosen to illustrate functional descriptions
provided in this document.
Figure 105. BMC/Power Reset Signals
23.1.1 Power Supply Interface Signals
The BMC controls the POWER_ON signal. It connects to the chassis power subsystem and is used to request power
state changes (asserted = request power on). The PS_PWRGD signal from the chassis power sub-system indicates
the current power state (asserted = power is on).
Figure 105 shows the power supply control signals and their sources. To turn the system on, the BMC asserts the
PS_ON signal and waits for the PS_PWRGD signal to assert in response, indicating that DC power is on.
The PS_PWRGD signal is normally asserted within 1.5 seconds, but the timeout interval can be set longer to add
flexibility in manufacturing test environments. The POWER_GOOD signal must remain stable and not glitch when
being asserted. The BMC uses the state of the PS_PWRGD signal to monitor whether the power supply is on and
operational, and to confirm whether the system power state matches the intended system on / off power state that was
commanded with the PS_ON signal.
23.1.2 Power-Good Dropout
Deassertion of the PS_PWRGD signal generates an interrupt that the BMC uses to detect either power sub-system
failure or loss of AC power. A power-good dropout is defined as the PS_PWRGD signal de-asserting when the system
should be in the DC power-on state as determined by the state of the PS_ON signal. The PS_PWRGD deassertion