Specifications

BIOS Error Handling QSSC-S4R Technical Product Specification
242
0 = ID is IPMB slave address
A
s a result, the generator ID byte will
go up in increments of 2 for events
logged by System Software Generator
IDs.
Sensor Type See the Intelligent Platform
Management Interface Specification,
Version 2.0.
0Fh – System Firmware Progress (formerly POST Error)
Sensor
number
Number of sensor that generated this
event.
06h – POST Error (BIOS)
Type code 6Fh if event offsets are specific to the
sensor.
6Fh – Sensor-specific Offset (event code)
Event Data 1 7:6
00b = unspecified byte 2
10b = OEM code in byte 2
5:4
00b = unspecified byte 3
10b = OEM code in byte 3.
The BIOS will not use encodings
01b and 11b for errors discussed in
this document.
3:0 Offset from Event Trigger for
discrete event state.
0xA0 – For a POST Error Code like FRB2 (0x8190), Event
Data 2 and Event Data 3 both contain “OEM codes”, so bits
7:6 and bits 5:4 both contain 10b (there is no Offset value in
this case)
Event Data 2 7:0 OEM code or unspecified. 90h – The LSB of the 'Watchdog timer failed on last boot'
error code 0x8190
Event Data 3 7:0 OEM code or unspecified. 81h – The MSB of the 'Watchdog timer failed on last boot'
error code 0x8190
21.3 POST Progress Codes and Errors
The system BIOS displays error messages on the video screen. Before video initialization, beep codes inform the user
of errors. POST error codes are logged in the event log. The BIOS displays POST error codes on the video monitor in
the Error Manager Window.
21.3.1 Diagnostic LEDs
During the system boot process, the BIOS executes several platform configuration processes, each of which is
assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the POST
code on the POST code diagnostic LEDs found on the back edge of the server board. To assist in troubleshooting a
system hang during the POST process, the diagnostic LEDs can be used to identify the last POST process to be
executed.
21.3.2 POST Code Checkpoints
Table 167. Post Codes and Messages
Pro
g
ress Code Pro
gr
ess Code Definition
Host Processor
0x10 Power-on initialization of the host processor (Boot Strap Processor)
0x11 Host processor cache initialization (including AP)
0x12 Starting application processor initialization
0x13 SMM initialization
Chipset
0x21 Initializing a chipset component
Memory
0x22 Reading configuration data from memory (SPD on DIMM)
0x23 Detecting presence of memory
0x24 Programming timing parameters in the memory controller
0x25 Configuring memory parameters in the memory controller
0x26 Optimizing memory controller settings
0x27 Initializing memory, such as ECC init