Specifications

QSSC-S4R Technical Product Specification BIOS Error Handling
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x Errors and warnings detected during POST, and logged as POST errors – these are discussed separately in
Section 21.2.2
Finally, there is one class of errors that may have been partially handled by BIOS in previous generations of Intel®
Server Boards, but no longer are:
x MA Sensors – these are now handled exclusively by the Operating System drivers and error-handling
mechanisms. This topic is not discussed here, since it is OS-specific and not handled by BIOS.
21.2.2 NMI on Fatal Errors
While most POR operating systems understand the Machine Check Architecture, there are still some operating
systems that need to escalate errors to NMI. The BIOS provides a setup option to facilitate such operating systems.
Note that when this option is selected, only those errors that are not routed to Machine Check are enabled for
escalation to NMI.
21.2.3 Error Logging via SMI Handler
The BIOS SMI handler is used to handle and log system level events that are not visible to the Server Management
firmware.
System events that are handled by the BIOS generate a Machine Check Exception (MCE) and an SMI. The BIOS SMI
handler sends a command to the BMC to log the event and provides the data to be logged. After the BIOS finishes
logging the error, it continues with a Machine Check Exception to report the condition to the OS (or if so configured,
may generate an NMI).
For example, the BIOS programs the hardware to generate an SMI on an Uncorrectable ECC Error from memory.
When this occurs, the SMI handler logs the location of the failed DDR3 DIMM in the BMC System Event Log. After the
BIOS finishes logging the error, it allows the Machine Check Exception to continue (or asserts an NMI if required).
21.2.3.1 PCI Express Sensors
The PCI Express* Specification includes standard error types that are defined under the Advanced Error Reporting
capabilities. The BIOS defines and owns sensors on a per-error basis. This provides greater decipherability of the SEL
entries, as well as better correlation between the actual error occurrence and the resultant SEL entry.
Intel
®
7500 Chipset supports up to 10 PCI Express ports. There is one link sensor per root port. In dual-IOH mode, the
number of root ports is 21 if the DMI link is configured as a root port.
The Intel® 82801Jx I/O Controller Hub (ICH10) has six PCI Express* root ports of link width x1 each, and tied to
D28:F0-5. The following table describes one method of assigning link numbers to ports.
The actual number of link numbers/ports is platform-specific.