Specifications

BIOS Role in Server Management QSSC-S4R Technical Product Specification
226
Of
f
set Name Length Value Description
0 = Reserved
Bits 2:0
0h = Unknown
1h = processor enabled
2h = processor disabled by user
3h = processor disabled by BIOS
4h = processor idle, waiting to be enabled
5h, 6h = Reserved
7h = Other
19h Processor
Upgrade
Byte 01h 01h – Other (code for LGA1366 has not been defined at this time).
1Ah L1 Cache Handle Word Varies Handle of the cache information structure for L1 cache for this processor.
Set to 0FFFFh if the cache information structure is not supported.
Offset Name Length Value Description
1Ch L2 Cache Handle Word Varies Handle of the cache information structure for L2 cache for this processor.
Set to 0FFFFh if cache information structure is not supported.
1Eh L3 Cache Handle Word Varies Handle of cache information structure for L3 cache for this processor. Set to
0FFFFh if cache information structure is not supported.
20h Serial Number Byte String String number for the serial number of this processor. This value is set by
the manufacturer and normally cannot be changed.
21h
A
sset Tag Byte String String number for the asset tag of this processor.
22h Part Number Byte String String number for the part number of this processor. This value is set by the
manufacturer and normally cannot be changed.
23h Core Count Byte Varies Number of cores per processor socket. If the value is unknown, the field is
set to 0. See the System Management BIOS Reference Specification,
Version 2.5, Section 3.3.5.6 for more information.
24h Core Enabled Byte Varies Number of enabled cores per processor socket. If the value is unknown, the
field is set to 0. See the System Management BIOS Reference
Specification, Version 2.5, Section 3.3.5.7 for more information.
25h Thread Count Byte Varies Number of threads per processor socket. If the value is unknown, the field
is set to 0. See the System Management BIOS Reference Specification,
Version 2.5, Section 3.3.5.8 for more information.
26h Processor
Characteristics
Word Bit Field Defines the functions supported by the processor.
20.5.2.6 Type 7 Structure — Cache Information
The SMBIOS Type 7 structure describes the attributes of the processor cache device(s) in the server. There is one
structure per cache device present in the server. For example, a server with two processors installed, each of which
has three levels of cache, has six Type 7 structures.
Table 152. SMBIOS Type 7 Structure
Of
f
set Name Length Value Description
00h Type Byte 7 Cache information indicator.
01h Length Byte 13h Number of bytes in this type structure.
02h Handle Word Varies The number of this structure in the table.
04h Socket
Designation
Byte String Number of the Null-terminated string. Same as associated processor.