Specifications

Operating System Boot, Sleep, and Wake QSSC-S4R Technical Product Specification
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Note: SATA SW RAID and EFI Optimized Boot are mutually exclusive options. SATA SWRAID can boot only in Legacy Boot mode.
For more information on the two options in the BIOS setup, see Section 17.2.3.3. and Section 17.2.3.3.4.
19.2.5 Intel® Turbo Boost Technology
Based on Intel® Xeon® 7500 series processor, QSSC-S4R supports the Intel® Turbo Boost Technology feature. This
feature allows the processor to run at a higher frequency than the marked processor frequency to increase
performance under certain conditions. For additional information, see Section 16.1.21.
However, the operation of Intel® Turbo Boost Technology is dependent on OS support for the feature. The Turbo
Boost operating state is only entered when the OS requests the highest (P0) performance state. By default, OS P-
state management engages Turbo Boost operation by requesting the P0 operating state. Newer OS releases that are
enabled for Turbo Boost Technology are able to use hardware feedback to drive P-state decisions more effectively.
19.3 Front Control Panel Support
The platform supports a power button, reset button, and NMI button on the control panel.
19.3.1 Power Button
The BIOS supports a front control panel power button. Pressing the power button initiates a request that the BMC
forwards to the ACPI power state machines in the chipset. It is monitored by the BMC and does not directly control
power on the power supply.
x Power Button — Off to On
The BMC monitors the power button and the wake-up event signals from the chipset. A transition from either
source results in the BMC starting the power-up sequence. Since the processors are not executing, the BIOS does
not participate in this sequence. The hardware receives the power good and reset signals from the BMC and then
transitions to an ON state.
x Power Button — On to Off (OS absent)
The System Control Interrupt (SCI) is masked. The BIOS sets up the power button event to generate an SMI and
checks the power button status bit in the ACPI hardware registers when an SMI occurs. If the status bit is set, the
BIOS sets the ACPI power state of the machine in the chipset to the OFF state. The BMC monitors power state
signals from the chipset and de-asserts PS_PWR_ON to the power supply. As a safety mechanism, the BMC
automatically powers off the system in 4 to 5 seconds if the BIOS fails to service the request.
x Power Button — On to Off (OS present)
If an ACPI OS is running, pressing the power button switch generates a request via an SCI to the OS to shut down
the system. The OS retains control of the system and the OS policy determines the sleep state into which the
system transitions, if any. Otherwise, the BIOS turns off the system.
19.3.2 Reset Button
The server platforms support a front control panel reset button. Pressing the reset button initiates a request that is
forwarded by the BMC to the chipset. The BIOS does not affect the behavior of the reset button.
19.3.3 NMI Button
The BIOS supports a front control panel NMI button. The NMI button may not be provided on all front panel designs.
Pressing the NMI button initiates a request that causes the BMC to generate an NMI (non-maskable interrupt). The
NMI is captured by the BIOS during boot services time, and by the OS during runtime. During boot services time, the
BIOS halts the system upon detection of the NMI.
19.4 Sleep and Wake Support
19.4.1 System Sleep States
The platform supports the following ACPI system sleep states:
x ACPI S0 (Working) state
x ACPI S1 (Sleep) state
x ACPI S5 (Soft-off) state