Specifications
BIOS Initialization QSSC-S4R Technical Product Specification
164
The SMI essentially intercepts the MCE, and the BIOS SMI handler reads the Platform Configuration Space Registers
(PCSR) to determine the error that occurred, and for memory errors to identify the DIMM that was the source of the
error.
The BIOS SMI handler reports the error by logging it to the SEL, and performs any other required actions. Then,
normally, the SMI handler does a RSM to return to MCE processing and allows the OS MCA handler to determine the
action to be taken by the OS.
The OS usually attempts to report an Uncorrectable Error in its own system logs, and then halts the system because
normal memory operations cannot continue and there is a risk of silent data corruption.
When NMI generation is enabled, the BIOS generates an NMI instead of returning to MCE processing. The NMI
generally serves the same purpose as the MCE, in that the OS NMI handler takes whatever action is necessary,
normally terminating in a system halt.
An NMI is not generated when the Uncorrectable Error merely results in a Loss of Redundancy in the Mirrored Mode.
In that case, the system is able to continue normal operations in a degraded non-redundant state.
The following table lists the conditions under which NMI generation occurs.
Table 100. NMI Generation Summary
Error Event Mode of Operation MCE NMI
Uncorrectable error occurs at
runtime
Maximum Performance
Mode
No Yes
Mirrored Mode Yes No
Spared Mode Yes No
16.2.12.2.7.1 OEM Override for NMI Generation Policy
Some operating systems do not understand Machine Check and cannot hence process the native Machine Checks
that are issued by the processor whenever there is a fatal memory error. The BIOS provides the ability to customize
the system for NMI generation on fatal errors. This setup option is available to OEM‘s but is not exposed in BIOS
setup. The OEM must request and use an Intel-provided utility to enable this feature if they need to use a legacy OS
that does not understand MCA.
16.2.12.3 Memory Error Handling Summary
Table 101. Memory Error Handling — POST
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Channel failed to train
in memory initialization
(if no other good
DIMMs are available to
continue system boot)
Generates
POST
Diagnostic
code
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generates
Memory
Error
Beep code
No SEL
records
generated
No
DIMM
fault
LEDs
lit
No
Status
LED
code
No SMBIOS
record
No Error Manager
error codes
System is halted