Specifications

QSSC-S4R Technical Product Specification BIOS Initialization
157
Event Data 2
Bits [3:0] Sparing Type
When ED2[7:4] = 0000b (Local Sparing Domain)
0000b – Reserved
0001b – DIMM Sparing
0010b – Rank Sparing
0011b - 1110b: Reserved
When ED2[7:4] = 0001b (Global Sparing Domain)
1111b - This field is unused and does not contain valid data.
Note: DIMM Sparing and Ranking sparing cannot co-exist.
Bits [7:4] Domain Instance Type
0000b: Local Memory Sparing Domain Instance
0001b: Global Memory Sparing Domain Instance
0010b-1111b – Reserved
If set to 0001b, this SEL pertains to a global memory sparing scheme where a spare
domain extends across entire sockets or memory boards, a subset as a spare unit for
another socket or subset thereof.
If set to 0000b, this SEL pertains to a local memory sparing domain that is restricted to
within a memory board only.
Note: Global Memory Sparing is not supported on QSSC-S4R Platform.
Event Data 3
Bit[7:4] Index of Spared Memory Board.
Bit [3] Reserved
Bits [2:0] Spared DIMM information
When ED2[7:4] = 0000b (Local Sparing Domain)
000b – DIMM_1B,where DIMM_1B lock step with DIMM_1D
001b – DIMM_1A,where DIMM_1A lock step with DIMM_1C
010b – DIMM_2B,where DIMM_2B lock step with DIMM_2D
011b – DIMM_2A,where DIMM_2A lock step with DIMM_2C
When ED2[7:4] = 0001b (Global Sparing Domain)
This field is not valid
Note: On QSSC-S4R platform Lock-step is enabled by default. So DIMM_1B/DIMM_1D,
DIMM_1A/DIMM_1C are in lock-step pair and so on.
Table 89. Formats of Memory RAS Configuration SEL Record for Memory Mirroring
Sensor Number Sensor Type Code Event/Reading
T
y
p
eCode
Description
0x12 0x0C 0x09 Memory RAS Configuration Information for Memory
Mirroring
Event Data 1
0x01 Memory Mirroring RAS Configuration Mode has been activated.
0x00 Memory Mirroring RAS Configuration Mode has been disabled
Event Data 2
A
lways 00h
Event Data 3
A
lways 00h