Specifications

BIOS Initialization QSSC-S4R Technical Product Specification
156
CPU4
MEM7_SLOT MEM8_SLOT
Table 87. Formats of Memory RAS State SEL Record for Memory Mirroring
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6[RG%QFG
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0x01 0x0C 0x0B Memory RAS State Information for Memory Mirroring
'XGPV&CVC
0xA0 Memory is configured in the Mirrored mode, and the memory is operating in the fully redundant state.
0xA1 Memory is configured in the Mirrored mode, and the memory has lost redundancy and is operating in the
degraded state.
Event Data 2
Bits [7:0] 0xFF – Reserved
Event Data 3
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Bits[7:5] Domain Instance Type
000b: Reserved
001b: Local memory mirroring domain instance (Intra-socket mirroring)
010b: Global memory mirroring domain instance across sockets (Inter-Socket mirroring)
011b - 111b: Reserved
Bits [4:0]
0-based Instance ID of this mirroring domain
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00000b {MEM1_SLOT, MEM2_SLOT} ,when Intra mirroring is enabled.
00001b {MEM3_SLOT, MEM4_SLOT}, when Intra mirroring is enabled.
00010b {MEM5_SLOT, MEM6_SLOT}, when Intra mirroring is enabled.
00011b {MEM7_SLOT, MEM8_SLOT}, when Intra mirroring is enabled.
00100b {MEM1_SLOT, MEM4_SLOT}, when Inter socket morroring is enabled and Hemishpere is disabled.
00101b {MEM3_SLOT, MEM2_SLOT}, when Inter socket morroring is enabled and Hemishpere is disabled.
00110b {MEM5_SLOT, MEM8_SLOT}, when Inter socket morroring is enabled and Hemishpere is disabled.
00111b {MEM7_SLOT, MEM6_SLOT}, when Inter socket morroring is enabled and Hemishpere is disabled.
01100b {MEM1_SLOT, MEM3_SLOT}, when Inter socket morroring is enabled and Hemishpere is enabled.
01101b {MEM2_SLOT, MEM4_SLOT}, when Inter socket morroring is enabled and Hemishpere is enabled.
01110b {MEM5_SLOT, MEM7_SLOT},when Inter socket morroring is enabled and Hemishpere is enabled.
01111b {MEM6_SLOT, MEM8_SLOT}, when Inter socket morroring is enabled and Hemishpere is enabled.
Table 88. Formats of Memory RAS State SEL Record for Memory Sparing
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0x11 0x0C 0x0B Memory RAS State Information for Memory Sparing
'XGPV&CVC
0xA0 Memory is configured in the Spare Mode, and the memory is operating in the fully
redundant state, with the spare unit inactive and available.
0xA1 Memory is configured in the Spare Mode, the memory has now failed over to the spare unit
and is operating in the degraded state, and the spare unit is now active and used up to
replace a failed unit.
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(See section 2.2.11.2.1.1 for Device Locator Interpretation)
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