Specifications

BIOS Initialization QSSC-S4R Technical Product Specification
154
BIOS Error Manager Screen The BIOS reports RAS configuration errors where the installed DDR3 DIMMs are
disabled because of population errors.
Beep Codes
The BIOS emits a beep code for cases where the s
y
stem has no memor
y
, or when
a fatal error like Memory BIST error is detected during memory discovery,
BIOS Setup Screen
RAS configuration errors are captured in the Advanced | Memor
y
screen in the
BIOS setup.
DIMM Fault Indicator LEDs The Intel® 7500 Chipset server boards that use the Intel® Xeon® 7500 processor
have a set of Fault Indicator LEDs on the board, one LED per DIMM socket. These
LEDs are used for indicating failed/faulty DDR3 DIMMs.
Note: If there is a fatal memory error in early POST, the DIMM Fault LED will not
be lit.
S
y
stem Fault/Status LEDs
Intel® 7500 Chipset server boards and systems that use the Intel® Xeon® 7500
processor provide a specific LED on the front panel that indicates the state of the
system. When a memory error occurs such that the performance of the memory
subsystem is affected, the BIOS sends a request to the BMC to light up the system
fault LED.
Note: If there is a fatal memory error in early POST, the System Fault LED will not
be lit.
NMI Generation
The BIOS triggers/initiates an NMI to halt the s
y
stem when a critical (or
uncorrectable) error occurs.
IPMI Memor
y
RAS
Configuration and State
Logging
The IPMI Memor
y
RAS events consist of a specific Memory RAS event and
configuration SEL entries that conform to the redundancy sensor definitions
described by the Intelligent Platform Management Interface Specification, Version
2.0.
16.2.12.2.1 IPMI Memory RAS Configuration and State Logging
Memory configuration logging refers to the BIOS sending the current RAS mode and RAS operational state to the BMC
to log the system memory RAS mode into the SEL as a SEL record. This allows a remote software/application to query
and retrieve the system memory state.
The memory configuration state sensors are “virtual” sensors. In other words, these sensors are owned and controlled
completely by the BIOS instead of an actual physical entity residing within the BMC.
The RAS configuration and state definitions are aligned with the definitions within the Intelligent Platform Management
Interface specification, Version 2.0. Accordingly, these sensors are read as “Entity” and “Redundant” sensors
(Event/Reading Type 0x09 and 0x0B respectively).
The BIOS-owned Type-3 SDR‘s corresponding to these sensors must include sensor assertion/deassertion to signify
change in the RAS configuration and states, as recommended by the IPMI specification. The BIOS will only record the
RAS configuration when it is modified. This is to conserve SEL space.
Table 84. Memory RAS Configuration and State SEL Records for Memory Mirroring
E
v
ent SEL
User enables
Mirrored mode
One SEL entry per mirror domain instance (Sensor Number 0x01) is created
to signify that the system just entered mirrored mode and is operating in the
fully- redundant state. ED1 = 0xA0
One global SEL entry (Sensor Number 0x12) to indicate that the system
has just entered the Mirrored RAS configuration mode.
System experiences
uncorrectable
memory errors and
one of the memory
board in the mirror
pair is taken offline.
One SEL entry for the specific mirror domain instance that has experienced
the error is created (Sensor Number 0x01) to signify that the system just lost
redundancy. ED1=0xA1