Specifications

BIOS Initialization QSSC-S4R Technical Product Specification

146

Note: The arrow points from Primary to Secondary

Copy of Memory Data

CPU1

MEM3_SLOT MEM4_SLOTMEM1_SLOT MEM2_SLOT

CPU4CPU3

MEM7_SLOT MEM8_SLOTMEM5_SLOT MEM6_SLOT

CPU2

Figure 71. Inter-Socket Mirroring

16.2.10.5 Hemisphere Mode

Intel® Xeon® 7500 processor has below components for each memory branch

x HA – Home Coherence Agent (BBOX)

x CA – Caching Agent for cores(SBOX)

x IMC – Integrated Memory Controller (MBOX)

In Hemisphere mode the Intel® Xeon® 7500 processor internally groups its cores and memory controllers into two

distinct groups called “hemisphere nodes”. Each hemisphere node will have its own Home Agent, Caching Agent and

IMC. This arrangement makes it possible for the processor to be viewed as two distinct ACPI resource domains. The

Hemisphere mode is a special processor mode that enables the processor to enable this form of partitioning. This

arrangement optimizes memory traffic from the cores so that they are always redirected to the closest home agent, and

hence the closest memory thereby improving performance. Hemisphere mode is special type of interleaving.

Interleaving should be enabled to make Hemisphere work.

The QSSC-S4R BIOS will enable Hemisphere mode by default if system memory configuration supports. The

Hemisphere mode will be disabled only when the user selects Intra Socket Mirroring. DIMMs need to be populated

identically across the nodes to enable Hemisphere mode. A minimum configuration to enable Hemisphere mode is to

populate identical DIMMs in Slots DIMM_1D & DIMM_1B of both MEM1_SLOT and MEM2_SLOT. BIOS enables

Hemisphere mode by default