Specifications

BIOS Initialization QSSC-S4R Technical Product Specification
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x Memory hot-plug can be supported in 2-way, 4-way or 8-way interleave mode but hot added memory will not be
interleaved.
BIOS setup will provide option for interleaving. When Memory RAS is set to Maximum Performance in setup, memory
is always interleaved across IMCs of same Socket along with Hemisphere mode if memory configuration supports for
better performance.
16.2.10.3 Sparing Mode
Sparing involves utilizing one of the DIMM pair or Rank pair as a spare unit, and failing over to that DIMM pair or Rank
pair when any of the other normal DIMM pair or Rank pair experiences errors beyond a pre-defined threshold. Sparing
does not provide redundant copies of memory and the system cannot continue to operate when an uncorrectable error
occurs. The purpose of Sparing is to detect a degrading DDR-3 DIMM before it causes a catastrophic shutdown.
Xeon® 7500 processor supports sparing at DIMM level as well as Rank level. The larger size DIMM pair or Rank pair
within an IMC branch can be assigned as spare memory in case of DIMM sparing or Rank sparing correspondingly.
Refer to the example shown for Minimal Optimal Population Upgrade for RAS modes in Section 16.2.8.2. When
number of correctable errors exceeds the threshold, BIOS shall initiate the migration of the failing DIMM pairs to spare
DIMM pairs or failing rank to spare rank and make the failed DIMM pair or rank inactive.
BIOS will provide option to enable or disable Sparing. See Section 17.2.3.3.1 for information about BIOS setup options
to enable this feature. The BIOS setup shows if sparing is possible with the current memory configuration.
SEL events are logged for Spare configuration, fail-over and redundancy lost events.
16.2.10.3.1 Computing Available memory
Available memory in system DIMM Sparing = Total installed memory – Size of the Spared DIMMs.
Available memory in system (Rank Sparing) = Total installed memory – Size of the Spared Ranks.
Rank Size = DIMM size / Num of Ranks
16.2.10.3.2 Minimum population for Sparing
Minimum population to Enable DIMM Sparing is {DIMM_1/B, DIMM_1/D} and {DIMM_1/A, DIMM_1/C}.
Minimum population to Enable Rank Sparing is dual Rank DIMMs {DIMM_1/B, DIMM_1/D}.
16.2.10.4 Mirroring Mode
The Mirroring Mode is a RAS feature in which two identical images of memory data are maintained, providing
maximum redundancy. On the Intel® Xeon® 7500 processor based QSSC-S4R server boards, the mirroring is
achieved across IMCs. The Intel® Xeon® 7500 processor alternates between both IMCs for read transactions. Write
transactions are issued to both IMCs under normal circumstances. The mirrored image is a redundant copy of the
primary image, and hence the system can continue to operate despite the presence of sporadic uncorrectable errors,
resulting in 100% data recovery.
Because the available system memory is divided into a primary image and a copy of the image, the effective system
memory is reduced by at least one-half. For example, if the system is populated with memory boards on MEM1_SLOT
and MEM2_SLOT each with two 1GB DIMMs. The total memory populated in the system is 4GB. However if mirroring
is enabled the effective system memory is reduced to 2GB.
The BIOS provides a setup option to enable mirroring if the current DIMM population is valid for the Mirrored mode of
operation. When memory mirroring is enabled, BIOS provides a setup option to select the mirroring mode between
Intra-socket and Inter-socket modes. During memory initialization, BIOS attempts to configure the memory mirroring as
selected in BIOS setup. If BIOS finds that the DIMM population is not suitable for mirroring mode selected, it falls back
to interleaving.
16.2.10.4.1 Intra-Socket Mirroring
In intra-socket mirroring mode, one IMC is mirrored with other IMC in each CPU socket. If the memory population
doesn‘t match between two IMCs of even one of the CPU sockets then BIOS will fail back to interleaving. On a fully
populated system, the mirror pairs will be {MEM1_SLOT, MEM2_SLOT}, {MEM3_SLOT, MEM4_SLOT},
{MEM5_SLOT, MEM6_SLOT} and {MEM7_SLOT, MEM8_SLOT}.