Specifications

QSSC-S4R Technical Product Specification BIOS Initialization
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16.2.10.1 Lock Step Mode.
Lock step mode is where cache lines are divided across lock step SMI links. Minimum one DIMM pair of same type
must be populated across the SMI channels to boot the system in lock step mode.
Figure 69. Lock step mode Example
BIOS will not provide any setup option to choose Lock Step Mode. BIOS will configure lock step mode by default and
DIMMs that does not follow to lock step mode rules will be disabled. In the above example, {DIMM 1/B, DIMM 1/D},
{DIMM 1/A, DIMM 1/C}, {DIMM 2/B, DIMM 2/D} and {DIMM 2/A, DIMM 2/C} are in lock step with each other.
16.2.10.2 Interleaving Mode
Interleaving works by dividing the system memory into multiple blocks. The most common numbers are two ,four or
eight, called two-way, four-way or eight-way interleaving, respectively
Memory interleaving increases bandwidth by allowing simultaneous access to more than one chunk of memory. This
improves performance because the processor can transfer more information to/from memory in the same amount of
time, and helps alleviate the processor- memory bottleneck that is a major limiting factor in overall performance.
The Intel® Xeon® 7500 processor provides intra and inter socket level interleaving.
16.2.10.2.1 Rank Interleaving
Rank Interleaving is NOT supported on the QSSC-S4R platform.
16.2.10.2.2 Intra Socket Interleaving
Intra socket Interleaving is to interleave cache-line data across the IMCs of same socket. Memory is interleaved in 2-
way in intra socket interleaving.
16.2.10.2.3 Inter Socket Interleaving
Inter socket Interleaving is to interleave cache-line data across the IMCs of other sockets. Memory is interleaved in 4-
way or 8-way in inter-socket (across IMCs across socket) level. If more than one processor sockets are populated, and
DDR-3 DIMMs are installed in slots to those sockets, the interleaved memory can spread across sockets. The process
is called Socket Interleave.
For more bandwidth and load distribution, Memory can be interleaved in 2/4/8-ways. Xeon® 7500 processor also
supports hemisphere interleaving (inter-socket). Interleaving also poses following restrictions,
x DIMM should be same type and size for any given interleaved memory region.