Specifications
QSSC-S4R Technical Product Specification BIOS Initialization
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27. If NUMA is enabled, BIOS can have only 2-way interleaving enabled or NO interleaving. Since 8-way, 4-way
interleaving is not supported along with NUMA.
28. If Inter Socket mirroring is enabled, BIOS can have only 2-way interleaving or None.
29. Inter Socket mirroring will be disabled when NUMA is enabled.
30. Inter socket mirroring across IOH is not supported. That means intersocket mirroring can happen only between
CPU1 and CPU2 OR CPU3 and CPU4.
31. Hemisphere mode can be enabled along with 2-way, 4-way or 8-way interleaving.
32. When NUMA is enabled, Hemisphere mode can have only 2-way interleaving option.
33. When NUMA is disabled, Hemisphere mode can have 2-way.4-way and 8-way interleaving option.
34. Hemisphere mode is enabled by default by BIOS if memory configuration supports, there will not be any BIOS
setup option to enable or disable Hemisphere Mode.BIOS will disable Hemisphere mode if memory
configuration not supported.
35. Hemisphere mode will be disabled if Interleaving is set to None.
36. Memory Module in windows OS Device Manager represents set of Risers that operate as one memory range.
For example, when BIOS has enabled 2-way interleaving, Device manager will show only four Risers, in case
of 4-way interleaving, Device manager will show only two Risers and only one Riser in case of 8-way
interleaving.
37. Whenever user changes memory HW configuration, if current memory configuration does not support already
configured memory RAS mode, BIOS will throw an error code 0xE4FC and restore the system to Maximum
performance mode.
x
16.2.8.2 Examples of DDR3 DIMM Population and Upgrade Rules
Figure 64. Minimum DDR-3 DIMM Population
x Minimum one DIMM pair of same type must be populated to boot the system.
x DIMMs must be populated as pairs, so that they are in lock step across SMI channels.
x Minimum DDR-3 DIMM configuration example is shown above.
x DIMM 1/B and DIMM 1/D are in lock step mode.
x This is also minimum configuration for Rank Sparing if DIMMS are dual rank or quad ranks.
x Sockets with empty DIMMs will use remote memory from the other socket and hence will function with latency.