Specifications

BIOS Initialization QSSC-S4R Technical Product Specification
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x The optimization techniques like lock step are used by the Intel® Xeon® 7500 processor to maximize memory
bandwidth.
Some guidelines must be followed when populating DIMMs. Below are DIMM population guidelines.
1. Minimum one Memory board with minimum one DIMM pair of same type must be populated to boot the system.
That is to say, pair DIMM 1/B and DIMM 1/D is minimum requirement to boot the system and system will be in
lock step mode.
2. DIMMs must be added as pairs, so that they are in lock step across SMI channels.
3. Quanta recommends DIMM population order as
{(DIMM_1B,DIMM_1D),(DIMM_1A,DIMM_1C),(DIMM_2B,DIMM_2D),(DIMM_2A,DI MM_2D)}. If this order is
not followed, BIOS will disable DIMMs which fail to follow this population order. Refer to Figure 63. QSSC-S4R
Memory DIMM Topology.
4. All DIMMs should be in lock step pair to work as recommended. And for DIMM {2/B, 2/D, 2/A, 2/C} to work
always the memory slots {1/B, 1/D, 1/A, 1/C} should be populated. Any other DIMM which don’t conform to the
above rules will be disabled.
5. Mixed memory DIMM is not supported on QSSC-S4R platform. Mixed DIMM includes mix of RDIMM and
UDIMM, mixed DIMM sizes and mixed DIMM technologies.
Note: Mixing DIMMs with different speeds on QSSC-S4R platform is not recommended.
6. Populate DIMMs farthest (DIMM 1/B, DIMM 1/D) to IMC first.
7. Quad rank must be populated first (farther) before dual and single rank to the memory board.
8. Maximum of four DIMMs\16 Ranks per Intel® SMI channel, 8 DIMMs per branch and 64 DIMMS per system.
9. If the DIMM 1/B and DIMM 1/D are NOT identical, then the system will fail to boot if system had only DIMM 1/B
and DIMM 1/D are populated to the memory board.
10. Memory Board containing UDIMM will be disabled by BIOS.
11. The minimal memory population for DIMM Sparing is {DIMM 1/B, DIMM 1/D, DIMM 1/A and DIMM 1/C} of a
memory board.
12. For DIMM Sparing memory population of adjacent lock-step DIMM pairs in DDR3 Buses should be identical.
13. In mirrored mode, both memory-boards should have same type of memory population.
14. The minimal memory population for intra socket Mirroring is {DIMM 1/B, DIMM 1/D} of both memory boards of
same socket.
15. The minimal memory population for inter socket Mirroring is pair of {DIMM 1/B, DIMM 1/D} inside two mirrored
memory boards.
16. Intra socket mirroring cannot be enabled with hemisphere mode and vice versa.
17. Inter socket mirroring can be enabled with hemisphere.
18. During inter socket mirroring with hemisphere, memory board 1 of Socket 1 and memory board 1 of Socket 2
will be mirror/slave. And memory board 2 of Socket 1 and memory board 2 of Socket 2 will be in slave/mirror.
19. In Max Performance Mode, memory will be interleaved across IMC/Memory Boards. However in Mirroring,
Memory Board Sparing and Hemisphere memory will not be interleaved across IMC/Memory Boards of the
Socket.
20. If an installed DDR3 DIMM has faulty or incompatible SPD data, it will be ignored during the Memory
Initialization and thus essentially disabled by the BIOS. If the DDR3 DIMM has no or missing SPD information,
the slot on which it is placed will be treated as empty by the BIOS.
21. If memory board 1 and 2 are empty, platform will still work with remote memory from memory board 1 or 2 from
other socket, provided that Socket is populated with an Intel® Xeon® 7500 processor.
22. Interleaving will be enabled only for Master Nodes not for Slave Nodes in mirroring mode.
23. If memory configuration does not support 8-way, 4-way or 2-way memory interleaving, that unsupported option
will not be listed in interleaving setup option.
24. During the memory discover phase of POST, the BIOS will disable any DDR3 DIMM that fails to conform to
these rules.
25. BIOS will display "Mirror Unit" for all DIMM, which are Mirror copy under Mirroring Mode.
26. BIOS will display "Spare Unit" for all DIMM, which are Spare DIMMs under Sparing Mode.