Specifications

QSSC-S4R Technical Product Specification BIOS Initialization
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Figure 62. QSSC-S4R System Memory Topology
Figure 63. QSSC-S4R Memory DIMM Topology and DIMM Population Order
16.2.8 Memory Sub-System Nomenclature
Intel® Xeon® 7500 processor has two Integrated Memory Controllers (IMCs). Each IMC has one Branch. Each Branch
is routed to a memory board socket and consists of two SMI (Scalable Memory Interconnect) channels. Each SMI
channels goes to an Intel® 7500 Scalable Memory Buffer (or Millbrook, the on-board memory buffer). The memory
board hosts two Millbrooks. Each Millbrook takes one SMI channel and produces two DDR3 Channels. Each DDR3
channel supports two DIMMs.
x DIMMs are organized into physical slots on DDR3 memory channels that belong to Memory boards (Risers).
x The DDR3 channels from Millbrook 0, Millbrook 1 are identified as Ch_0 and Ch_1.
x Each Socket can support a maximum of 16 DIMM sockets (8 DIMMs per Board, 2 Boards per Socket).
x Sockets are self-contained and autonomous. However all RAS, Error Management, etc configuration in BIOS setup
will be applied common across sockets.
16.2.8.1 Memory Upgrade Rules
Upgrading the system memory requires careful positioning of the DDR-3 DIMMs, based on the following factors:
x The current RAS mode of operation.
x The existing DDR3 DIMM population.
x The DDR3 DIMM characteristics.