Specifications

BIOS Initialization QSSC-S4R Technical Product Specification
136
16.2.4.1 Processor Cores, QPI Links and DDR3 Channels Frequency Configuration
The Intel® Xeon® 7500 series processor connects to other Xeon® 7500 processors and to Intel® 7500 Chipset
through Intel® Quick Path Interconnect (QPI) technology. The frequencies of the processor cores and the QPI links of
Intel® Xeon® 7500 processor are independent from each other. Unlike Front-Side Bus (FSB) architecture of previous
Intel® Xeon® processor generations, there are no fixed-ratio frequency requirements for the Intel® 7500 processor.
The Intel® 7500 Chipset supports 4.8 GT/s, 5.86 GT/s and 6.4 GT/s frequencies for the QPI links. During QPI
initialization, the BIOS configures both endpoints of each QPI link to same supportable speeds for the correct
operation.
Depending on the processor model, the Intel® Xeon® 7500 Processor Series package may have an Integrated
Memory Controller capable of 800, 1066, or 1333 MHz operation. The speed of the IMC will be a limiting factor in
choosing an operating frequency for the memory subsystem.
During memory discovery, the BIOS keeps track of the latency requirements of each installed DDR3 DIMM by
recording relevant latency requirements from each DDR3 DIMM‘s SPD data, as described in Section 16.2.4.
Taking into account the speed of the Integrated Memory Controller in the processor .The BIOS first arrives at a highest
common frequency that matches the requirements of all components and then configures the memory system and the
DDR3 DIMMs for that common frequency. The entire system all SMI channels on four processor sockets will be
configured to run at a single common memory channel frequency.
16.2.5 Memory Test
16.2.5.1 Integrated Memory BIST Engine
The IMC in Intel® Xeon® 7500 series processor incorporates an integrated Memory Built-in Self Test (BIST) engine
that is enabled to provide extensive coverage of memory errors at both the memory cells and the data paths emanating
from the DDR3 DIMMs.
The BIOS uses this Memory BIST engine to perform two specific operations:
x ECC fill to set the memory contents to a known state. This provides a bare minimal error detection capability, and
is referred to as the Basic Memory Test algorithm.
x Extensive DDR3 DIMM testing to search for memory errors on both the memory cells and the data paths. This is
referred to as the Comprehensive Memory Test algorithm.
The Memory BIST engine replaces the traditional BIOS-based software memory tests. The Memory BIST engine is
much faster than the traditional memory tests. The BIOS also uses the Memory BIST to initialize memory at the end of
the memory discovery process.
16.2.6 Memory Scrub Engine
The IMC in Intel® Xeon® 7500 processor incorporates a “Memory Scrub” engine. When this integrated component is
enabled, it performs periodic checks on the memory cells, and identifies and corrects single-bit errors. Two types of
scrubbing operations are supported:
x Demand scrubbing – executes when an error is encountered during normal read/write of data.
x Patrol scrubbing – proactively walks through populated memory space seeking soft errors. Patrol Scrubbing is
disabled when Memory Mirroring or Sparing is enabled. In QSSC-S4R, patrol scrub is performed at periodic
interval.
There is no BIOS setup option available to Enable or Disable Demand Scrub or Patrol Scrub. Patrol Scrub is always
enabled by the BIOS, independent of mirroring mode. On Xeon® 7500 processor, Demand Scrub is automatically
enabled and used by the chipset. Since demand scrub can not function when mirrored mode is enabled, CPU
automatically auto-disables Demand Scrub when it is configured in the mirrored mode.
The BIOS programs the Patrol Scrub interval for a complete memory scrub operation in 24 hours. This depends on the
total size of installed memory and common clock cycle for memory transactions.
16.2.7 Memory Map and Population Rules
The following nomenclature is followed for DIMM population.