Specifications

QSSC-S4R Technical Product Specification BIOS Initialization
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Any of the above errors also signal a memory error beep code. Memory beep code errors are described in Section
21.3.4.
16.2.3 Displaying System Memory
x The BIOS displays the “Total Memory” of the system during POST if Quiet Boot is disabled in the BIOS setup. This
is the total size of memory discovered by the BIOS during POST, and is the sum of the individual sizes of installed
DDR3 DIMMs in the system.
x The BIOS displays the “Effective Memory” of the system in the BIOS Setup. The term Effective Memory refers to
the total size of all DDR3 DIMMs that are active (not disabled) and not used as redundant units.
x The BIOS provides the total memory of the system in the main page of the BIOS setup. This total is the same as
the amount described by the first bullet above.
x If Quiet Boot is disabled, the BIOS displays the total system memory on the diagnostic screen at the end of POST.
This total is the same as the amount described by the first bullet above.
x The BIOS builds an SMBIOS OEM Type 131 “OEM Memory Information” structure, including bitmaps of DIMM
slots available, installed DIMMs, mapped out (disabled) DIMMs, and DIMMs involved in Mirrored Mode RAS. For
details of the Type 131 structure, refer Section Error! Reference source not found..
x The BIOS provides the total amount of memory in the system by supporting the EFI Boot Service function,
GetMemoryMap().
x The BIOS provides the total amount of memory in the system by supporting the INT 15h, E820h function. For
details, see the Advanced Configuration and Power Interface Specification, Revision 3.0b for details.
16.2.3.1 Memory Reservation for Memory-mapped Functions
A region of size 40 MB of memory below 4 GB is always reserved for mapping chipset, processor and BIOS (flash)
spaces as memory-mapped I/O regions. This region appears as a loss of memory to the OS.
This reserved region is reclaimed by the OS if PAE enabled in the OS.
In addition to this memory reservation, the BIOS creates another reserved region for memory-mapped PCI Express
functions, 256 MB of standard PC Express* Memory Mapped I/O (MMIO) configuration space.
If this is set to “Enabled”, the BIOS maximizes usage of memory below 4 GB for an OS without PAE capability by
limiting PCI Express Extended Configuration Space to 64 buses rather than the standard 256 buses. This is done using
the MAX_BUS_NUMBER feature offered by the Intel® 7500 I/O Hub and a variably sized Memory Mapped I/O region
for the PCI Express functions.
16.2.3.2 High-Memory Reclaim
When 4 GB or more of physical memory is installed (physical memory is the memory installed as DDR3 DIMMs), the
reserved memory is lost. However, the Intel® 7500 I/O Hub provides a feature called High-memory reclaim, that allows
the BIOS and the OS to remap the lost physical memory into system memory above 4 GB (the system memory is the
memory that can be seen by the processor).
The BIOS always enables high-memory reclaim if it discovers installed physical memory that is equal to or greater than
4 GB. For the OS, the reclaimed memory can be recovered only if the PAE feature in the processor is supported and
enabled. Most operating systems support this feature. For details, see the relevant OS manuals.
16.2.3.3 ECC Support
QSSC-S4R does not support UDIMMs, only RDIMMs are supported. RDIMMs will have ECC support; therefore ECC
support is always present on QSSC-S4R platform.
16.2.4 Support for Mixed-speed Memory Modules
The BIOS supports memory modules of mixed speed by automatic selection of the common frequency that will support
all installed DDR3 DIMMs. Each DDR3 DIMM advertises its supported clock speed via the TCKMIN parameter in its
Serial-Presence Data (SPD). The BIOS uses this information to arrive at the common highest frequency that satisfies
the processor Integrated Memory Controller speed and the speeds of all installed DDR3 DIMMs.
Mix of RDIMM and UDIMM, mix DIMM sizes and mix DIMM technologies are not supported on the QSSC-S4R
platform.
Note: Quanta does not recommend mixing DIMMs with different speeds on QSSC-S4R platform.