Specifications

BIOS Initialization QSSC-S4R Technical Product Specification
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The BIOS configures the memory system dynamically in accordance with the available DDR-3 DIMM population and
the selected RAS (Reliability, Availability and Serviceability) mode of operation.
QSSC-S4R supports only RDIMMs.
Figure 61. Memory Topology
16.2.1 Memory Sizing and Configuration
The BIOS supports various memory module sizes and configurations. These combinations of sizes and configurations
are valid only for DDR3 DIMMs. The BIOS reads the Serial Presence Detect (SPD) SEEPROMs on each installed
memory module (DDR3 DIMMs) to determine its size and other characteristics. The memory-sizing algorithm then
determines the cumulative size of each row of DDR3 DIMMs. The BIOS programs the IMC in the Intel® Xeon® 7500
series processor accordingly, such that the range of memory accessible from the processor is mapped into the correct
DDR3 DIMM or a set of DDR3 DIMMs.
The BIOS supports DRAM sizes of 512 MB, 1 GB, 2 GB, 4GB and 8 GB.
16.2.2 POST Error Codes
The range {0xE0 - 0xEF} of POST codes is used for memory errors in early POST. In late POST, same range is used
for reporting other system errors.
x No Usable Memory Error: If no memory is available, the system emits POST Diagnostic LED code 0xE1 and
halts the system.
x Configuration Error: If a DDR3 DIMM has no SPD information at all, the BIOS treats the DDR3 DIMM slot as if no
DDR3 DIMM is present on it. If all installed DIMMs in the system have SPD errors, the BIOS will report complete
failure, and produce the same result as the “No Usable Memory” case as above.
x Memory Test Error: If a DDR3 DIMM or a set of DDR3 DIMMs on the same memory channel (row) fails Memory
BIST but usable memory remains available, the BIOS emits the memory error beep code.
x Channel Training Error: If the memory initialization process is unable to properly perform the DQ/DQS training on
a memory channel, but usable memory remains available, the BIOS emits a beep code.
x Invalid Error: If the BIOS detects that all installed DIMMs in the system are UDIMMs, then it will emit the memory
error beep code and display POST Diagnostic LED code 0xED. It will then halt.
During above errors, if there is usable memory on other memory boards, BIOS will continue POST and eventually
reporting the error in the BIOS Error Manager. The BIOS will also report this error to the SEL as a POST Progress
Error. However, if the error results in no usable memory in the system, or if the error during memory discovery is fatal
such that no usable memory is available, the BIOS will halt with POST Diagnostic LED displayed. POST Diagnostic
LED codes are listed in Section 21.3.1. Under this fatal error condition, no BMC SEL will be logged.