Specifications

BIOS Initialization QSSC-S4R Technical Product Specification
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Error Severity System Action
Population
Rule
Violation
x Logs the error in the SEL
x Does not disable any processors if possible.
x Displays “019C: Generic Processor Population Error”
x Continues to boot normally on to the OS.
16.1.11 Intel® Hyper-Threading Technology
The QSSC-S4R BIOS detects processors that support Intel® Hyper-Threading Technology (Intel® HT Technology)
and enables the feature during POST. Most of the Intel® Xeon® 7500 processor SKU supports this feature. If the
processor supports this feature, the BIOS Setup provides an option to enable or disable it. The default is enabled.
16.1.12 Enhanced Intel SpeedStep® Technology
Intel® Xeon® processors support the Geyserville3 feature of the Enhanced Intel® SpeedStep technology. This feature
changes the processor operating ratio and voltage similar to the Thermal Monitor 1 (TM1) feature. The BIOS
implements the Geyserville3 feature in conjunction with the TM1 feature. The BIOS enables a combination of TM1 and
TM2 according to the processor BIOS Writer's Guide.
16.1.13 Intel® 64 Instruction Set Architecture (Intel® 64)
The system BIOS does the following:
x Detects whether the processor is Intel® 64 capable.
x Initializes the SMBASE for each processor.
x Detects the appropriate SMRAM State Save Map used by the processor.
x Enables Intel® 64 during memory initialization, if necessary.
16.1.13.1 Method to Identify Intel® 64 Capability
The extended feature flags returned by the CPUID instruction contain the following information:
x Execute CPUID instruction with EAX = 80000001h
x Check the Intel® 64 feature flag in EDX[29]:
x If 0, then the processor is not Intel® 64 capable.
x If 1, then the processor is Intel® 64 capable.
16.1.13.2 Activating and Deactivating Intel® 64
The BIOS activates Intel® 64 mode in order to support native x64 EFI, as described by the UEFI Specification.
16.1.13.3 Initializing SMBASE
The BIOS initializes SMBASE for each processor during POST.
x If the processor is Intel® 64 capable, then the BIOS must ensure that the SMBASE between each processor is >=
300h.
x If the processor is not Intel® 64 capable, then the BIOS must ensure that the SMBASE between each processor is
>= 200h.
To simplify the functionality, the BIOS allocates 400h gaps between SMBASEs. This satisfies the required space for
both cases.
16.1.14 Execute Disable Bit Feature
The Execute Disable Bit feature (XD bit) can prevent data pages from being used by malicious software to execute
code. A processor with the XD bit feature can provide memory protection in one of the following modes:
x Legacy protected mode if Physical Address Extension (PAE) is enabled.
x Intel® 64 mode when 64-bit extension technology is enabled (Entering Intel® 64 mode requires enabling PAE).
The XD bit does not introduce any new instructions, it requires operating systems to operate in a PAE-enabled
environment and establish a page-granular protection policy for memory. The XD bit can be enabled and disabled in
the BIOS Setup. The default behavior is enabled.