Specifications

BIOS Initialization QSSC-S4R Technical Product Specification
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Table 79. CPU Population Rules for QSSC-S4R
Number of CPUs CPU1 CPU2 CPU3 CPU4
1
9
X X X
2
9
X
9
X
2
9
9
X X
3
9
9
9
X
4
9
9
9
9
1. In one CPU configuration, always populate CPU1
x This will ensure that the primary CPU socket is always populated.
2. In two CPU configuration, populate CPU1 and CPU3
x This ensures full I/O connectivity and hence maximum I/O availability
x An alternate, reduced I/O 2-S population is also supported. This population consists of CPU1 and CPU2. As
CPU3 which shall connect to IOH2, is not populated, PCIe slot 5 – 9 will not be supported or functional.
3. In three CPU configuration, populate CPU1, CPU2 and CPU3
4. In four CPU configuration, populate CPU1, CPU2, CPU3 and CPU4.
16.1.4 Mixed Processor Steppings
For optimum performance, only identical processors should be installed in a server. However, processor steppings
within a common processor family can be mixed as long as they are listed as compatible in the Intel® Xeon®
Processor Specification Updates published by Intel Corporation – typically mixing only processors that are plus or
minus one stepping from each other.
16.1.5 Mixed Processor Families
Processor families cannot be mixed in a server.
16.1.6 Mixed Processor Intel® QuickPath Interconnect Speeds
Processors with different Maximum Core Frequencies and Maximum Intel® QuickPath Interconnect Speeds can be
mixed in a system. If this condition is detected, all processor speeds are set to the highest common speed.
16.1.7 Mixed Processor Cache Sizes
If the installed processors have mixed cache sizes, an error is reported. The size of all cache levels must match
between all installed processors.
16.1.8 Processor Cache
The BIOS enables all levels of processor cache as early as possible during POST. There are no user options to modify
the cache configuration, size, or policies. All caches detected are reported in the BIOS Setup.
16.1.9 Microcode Update
If the system BIOS detects a processor for which a microcode update is not available, the BIOS reports an error. IA-32
processors can correct specific errata by loading an Intel-supplied data block, known as a microcode update. The BIOS
stores the update in non-volatile memory and loads it into each processor during POST. The BIOS allows a number of
microcode updates to be stored in the flash. This is limited by the amount of free space available. The system BIOS
supports the real mode INT15, D042h interface for updating the microcode updates in the flash.
16.1.10 Mixed Processor Configuration
The following table describes mixed processor conditions and recommended actions for QSSC-S4R server boards and
systems that use the Intel® 7500 Chipset. Errors fall into one of three categories:
x Fatal: If the system can boot, it pauses at a blank screen with the text “Unrecoverable fatal error found. System will
not boot until the error is resolved” and “Press <F2> to enter setup”, regardless of whether the “Post Error Pause”
setup option is enabled or disabled. When the operator presses the <F2> key on the keyboard, the error message
is displayed on the Error Manager screen, and an error is logged to the System Event Log (SEL) with the error