Specifications

QSSC-S4R Technical Product Specification BIOS Initialization
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16. BIOS Initialization
16.1 Processors
QSSC-S4R server boards are four socket boards that may have one, two, three or four processors installed. When a
single processor is installed, it must be installed into CPU Socket 1.
16.1.1 CPUID
Intel® Xeon® 7500 series processor and its next generation processor (Westmere-EX) are supported on QSSC-S4R.
The processors are identified by their “CPUID” values:
x Intel® Xeon® 7500 Processor series: CPU ID – 0x000206Exh
x Intel’s next generation processor series (Westmere-EX): CPU ID – 0x000206Fxh
(“x” above represents a hex digit identifying the “Stepping”, or revision ID, of the processor.)
16.1.2 Multiple Processor Initialization
IA-32 processors have a microcode-based bootstrap processor (BSP) arbitration protocol. The BSP starts executing
from the reset vector (F000:FFF0h). A processor that does not perform the role of BSP is referred to as an Application
Processor (AP).
The QSSC-S4R 4S Platform is a quad-processor socket server platforms designed around the new Intel® QuickPath
Interconnect (QPI), which replaces front-side bus architecture.
The processors themselves are multi-core processor packages, so the number of discrete processor cores is a function
of the number of processor packages times the number of cores per package. For a quad - processor socket board
with eight-core processors, there will be thirty-two logically separate processor cores. And with Intel® Hyper-Threading
enabled, there will be sixty-four processing cores.
At reset, one core from each processor socket becomes the Package BSP (PBSP) and the rest of the cores in the
socket go into a wait for SIPI state.
The PBSPs in the system contend for System BSP (SBSP) stature. The IOH to which the ICH is connected is known
as the Legacy IOH (LIOH). On the QSSC-S4R platform, CPU1 and CPU2 are physically connected to the LIOH (IOH1),
and CPU3 and CPU4 are connected to the non-Legacy IOH (IOH2). CPU1 and CPU2 will race for SBSP. Once a CPU
becomes the SBSP, it performs topology discovery. The SBSP then initializes the rest of the system. CPU3 and CPU4
will never race for SBSP stature. Instead, when they are powered on, they will automatically assume AP stature.
The SBSP is responsible for executing the BIOS POST and preparing the server to boot the OS. At boot time, the
server is in virtual wire mode and the BSP alone is programmed to accept local interrupts - INTR driven by
programmable interrupt controller (PIC) and non-maskable interrupt (NMI).
As a part of the boot process, the BSP wakes each AP. When awakened, an AP programs its memory type range
registers (MTRRs) to be identical to those of the BSP. All APs execute a halt instruction with their local interrupts
disabled. If the BSP determines that an AP exists that is a lower-featured processor or that has a lower value returned
by the CPUID function, the BSP stature switches to that lowest-featured processor in the server.
As a part of the multi-processor initialization process, each AP will also load microcode.
Note: There is a very low-probability system hang that could potentially occur during this switching of BSP responsibility. If the AP
does not respond, or quits responding during POST, the system hangs since the QPI links terminate. Due to the nature of this hang,
there is no means to issue a message or an error code. Both processors remain in wait states.
16.1.3 CPU Population
CPU population rule for QSSC-S4R server platform is described in the table below. If the CPU sockets are populated in
a non-Quanta recommended manner, BIOS behavior is non-deterministic and not validated.
Note: Quanta recommends only using the following CPU population guidelines: