Specifications

Power Distribution Board (PDB) QSSC-S4R Technical Product Specification
118
Figure 58. Power Sub-system Efficiency in Cold Redundant Operation
The table below lists the PSs that would be enabled in different power ranges:
Table 66. PS Enabled in Power Range
Power
range
0<P<P
1
P
1
<P<P
2
P
2
<P<P
3
P
3
<P<P
4
Condition P
1
<P
max
Eff(PS1)
>Eff(PS1+PS2),
Eff (PS1) >
Eff(PS1+PS2+PS3)
Eff (PS1) >
Eff(PS1+PS2+PS3
+PS4)
Eff(PS1+PS2) >
Eff(PS1),
Eff(PS1+PS2) >
Eff(PS1+PS2+PS3)
Eff(PS1+PS2) >
Eff(PS1+PS2+PS3
+PS4)
Eff(PS1+PS2+PS3) >
Eff(PS1)
Eff(PS1+PS2+PS3) >
Eff(PS1+PS2)
Eff(PS1+PS2+PS3) >
Eff(PS1+PS2+PS3+
PS4)
Eff(PS1+PS2+PS3+
PS4) > Eff(PS1)
Eff(PS1+PS2+PS3+
PS4) >
Eff(PS1+PS2)
Eff(PS1+PS2+PS3+
PS4) >
Eff(PS1+PS2+PS3)
PS
enabled
PS1 PS1, PS2 PS1, PS2, PS3 PS1, PS2, PS3, PS4
PS_FORCEPR_N
#
The PS_FORCEPR_N signal (pin 24 of the PDB 2 x17 connector), which gets asserted at the following power levels:
1PS: 1Pnom (no redundancy)
2PSs: 1.9 Pnom (no redundancy)
3PSs: 2.8Pnom (no redundancy)
4PSs: 2.8Pnom (3+1 redundancy)
13.3.3 Cold Redundancy Disabling Feature
Cold redundancy operation is turned on as default configuration but/and can be disabled by hardware – via Jumper
and/or firmware – via PMBus. The location of this cold redundancy jumper is identified as in Table 52. Power
Distribution Board Connector Location.